1. Introduction Intelligent measurement and control circuit systems have been widely used in industrial control and various consumer electronics products. They are generally based on a microcontroller, supplemented by analog signal conditioning, analog-to-digital conversion, human-machine interface (including buttons and digital displays), power output, and other components, as shown in Figure 1. Measurement and control systems are designed based on PCB boards, resulting in large size and power consumption. Especially in order to enable the system to operate in various harsh environments, designers typically spend a significant amount of time and effort researching and implementing various hardware and software anti-interference measures. Furthermore, these systems share many commonalities, leading to repetitive work for designers. 2. System Structure With the rapid development of integrated circuit design technology and deep submicron manufacturing technology, integrated circuits have entered the era of system-on-a-chip (SoC), and have fully transitioned from digital SoCs to mixed-signal SoCs. This paper aims to integrate the signal acquisition, conversion, storage, processing, and I/O functions required by the intelligent measurement and control system into a single-chip system. Highly integrated single-chip devices are lower in cost, consume less power, and occupy less area than discrete ICs; they also simplify PCB system design and improve the system's anti-interference capability. System-on-a-chip (SoC) applications are simple and versatile. Users only need to connect different sensors and a few components to form a complete measurement and control system, shortening the product's time to market. A general measurement and control system is shown in Figure 1. To ensure the single-chip intelligent measurement and control system has good versatility, we adopted a design scheme based on a microcontroller core. The SoC includes a microcontroller, instrumentation amplifier circuit, A/D converter, EEPROM, ROM, RAM, and drive logic, etc. 2.1 Microcontroller Core In industrial control and various low-to-mid-range consumer electronics products, 8-bit microcontrollers still account for a considerable proportion and will remain so for a considerable period of time. Their implementation technology is mature and their structure is simple. According to the instruction set, microcontrollers can be divided into several types, such as CISC, RISC, and RISC-like. CISC has high code density, but most instructions require multiple clock cycles to complete, making implementation relatively complex. RISC hardware implementation is relatively simple, but its code density is low; RISC-like types have the characteristics of high code density and single-cycle instruction completion. Based on the above considerations, we independently developed an 8-bit RISC-like microcontroller IP soft core, the block diagram of which is shown in Figure 2. To utilize existing compilation tools, the microcontroller's instructions are compatible with those of the Microchip PIC16C62 microcontroller. The microcontroller has 35 single-word, single-cycle 14-bit instructions; all instructions except program branch instructions are single-cycle instructions. It adopts a Harvard architecture with a two-stage pipeline design. It features three types of interrupt sources: pin level change interrupt, external edge interrupt, and timer interrupt, and an 8-level hardware stack. 2.2 A/D Converter A/D converters come in various types, including parallel, successive approximation, and integrating types, each with its own advantages and disadvantages and capable of meeting different specific application requirements. In most industrial measurement and control and consumer product applications, time quantities are on the order of milliseconds, but high accuracy, extremely high reliability, and strong anti-interference capabilities are required. Therefore, a dual-slope integrating A/D converter was chosen to implement the analog-to-digital conversion function. The structure of the designed dual-slope integrating A/D converter is shown in Figure 3, and its signal control timing is shown in Figure 4. To reduce the influence of integrator offset drift, a compensation measurement method is adopted, and electronic switches S3 and S4 and a zero-drift memory capacitor are set in the circuit. Let the input signal be Vi, and the reference voltage be -Vr. The dual-slope A/D converter operates in three stages: First, the zero-compensation period: switches S3 and S4 are turned on, and S1 and S2 are turned off. The integrator's open-loop gain is very large, so its output is essentially equal to the comparator's offset voltage e2. Second, the signal timing integration stage: switch S1 is turned on, and S4, S3, and S2 are turned off, integrating the measured voltage within a fixed time. At the initial instant, the integrator's output is e2. Therefore, the integrator starts integrating from e2, and after time Td, it enters the third stage, at which point the integrator's output is... Third, the reverse integration stage: switch S2 is turned on, and S3 and S1 are turned off, connecting the integrator to the reference voltage. When the integrator's output returns to e2, the comparator flips. Let the time of this integration interval be Tx. It can be seen that the entire integration process is unaffected by offset and drift. Assuming the counts of the signal timing integration and the reference inversion stage counters are N1 and N2 respectively, then N2 = Vi * N1 / Vr. In this system, N1 = 10000 and Vr = 1.0000V. The sampling result expression is independent of the clock frequency and the integrating resistor and capacitor, and depends only on the reference voltage. By taking the counter clock frequency as an integer multiple of the power frequency signal, the integration time of the signal is an integer multiple of the power frequency period, which can minimize the error caused by power frequency noise, thereby effectively suppressing power frequency interference from the power grid. The counter uses the CPU's TMR1, which is a 16-bit timer/counter composed of two registers, TMR1H and TMR1L, and is incremented by 1. To facilitate interfacing with the A/D converter, a comparator output gate signal BUSY is added to the standard TMR1. The initial count value of the timer is set to 0xd8ef, so that the counter value will become zero after the timing integration stage, and the counter value after the inversion integration stage is the sampling result. The A/D conversion is initiated by sending a pulse through I/O port RB1. After the conversion is complete, the BUSY signal stops the counting and requests an interrupt from the CPU. The sampled value is read and the A/D conversion is restarted in the interrupt routine. The BUSY signal, S3/S4, and the counter's count value are controlled by the acquisition timing control logic module to control switches S1 and S2. 2.3 Storage Unit To facilitate the use of the microcontroller, a 2K×14bit program storage unit and a 128×8bit data storage unit are designed. Additionally, a certain amount of EEPROM is integrated to meet the input and modification of system parameters, such as sensor scaling coefficients and control algorithm program parameters. 2.4 Implementation of Expansion Ports In practical applications, some special IP modules may be integrated around the microcontroller. Communication between the IP modules and the microcontroller is achieved through the microcontroller's addressing mode. Data access to the IP modules is achieved by reading and writing to the addressable units of the IP modules. A unique address unit is assigned to each IP module to ensure the uniqueness of its data access. The integration of multiple IP modules may significantly increase the number of ports on the chip. For the ports of external modules, the method of multiplexing with the general I/O ports of the microcontroller can be adopted. 2.5 Output Display Digital Tube has the advantages of long life, corrosion resistance, vibration resistance, explosion-proof and moisture-proof, high reliability and wide viewing angle, and is widely used in various measurement and control instruments. The digital tube is dynamically refreshed by using the timer interrupt method of the microcontroller. 2.6 Low Power Design In order to meet the low power consumption requirements of portable measurement and control systems, the power consumption reduction requirements must be fully considered in the design. The microcontroller has a SLEEP instruction. Before the SLEEP state, the microcontroller can turn off the power supply of the sensor, the pre-amplifier circuit and the reference power supply. In addition, in the logic design, gated clock, asynchronous logic and glitches are used to reduce power consumption. 3 Simulation and Design 3.1 System Simulation First, the software program of the microcontroller core is written into assembly or C language code, and then the HEX file is generated by the PIC16C62 compilation system. In order to be usable by EDA tools, we convert the HEX file into a Verilog type file. The method involves analyzing the generated HEX file format and converting it into a .v file using the VB6.0 high-level language, with the implementation using case statements. The waveform below is generated using ACTIVE-HDL4.2 simulation. An interrupt is generated on the falling edge of the portbinout(0) signal (from the BUSY signal). In the interrupt, the count value is read out and the TMR1 timer is reassigned to 0xd8ef. The read value is then output bit by bit using PORTC in HEX format. 3.2 Hardware Verification Platform To verify the system's functionality, a hardware simulation system combining FPGA and general-purpose components was designed. The microcontroller core, ROM, RAM, digital part of the A/D conversion, and the logic part of the digital tube driver are implemented using FPGA logic, while the analog part is implemented using general-purpose components. The block diagram is shown in Figure 3. The FPGA uses Xlinx's 100,000-gate XC2S100, and the program memory and register RAM are implemented using its on-chip BlockRAM. The FPGA's programming file is stored in a PROM. The operational amplifier is implemented using three OP07 chips to form an instrumentation amplifier; the analog section of the A/D converter is constructed using operational amplifiers and resistor-capacitor components. 3.3 System Design After system verification, the back-end layout design was carried out. The back-end design converts the circuit representation of each component into a set representation, and the nets connecting the components are also converted into geometric connection diagrams. To reduce the scale of the problem, we first divide the system into several modules, including digital, ROM and RAM, and analog sections, and then select a good layout scheme for each module and the entire chip. Next, we complete the interconnection between modules and further optimize the routing results. Finally, we perform compression to complete the post-routing optimization process, further reducing the chip area. 4 Conclusion This paper describes the design method of intelligent measurement and control integrated circuits. The design process fully considers the general requirements of intelligent measurement and control, emphasizing versatility, so that the intelligent measurement and control system chip only needs a few external components to form a measurement and control system. The design verification based on an FPGA system was also conducted. Several issues that need to be considered during the design process were analyzed in detail, such as the selection of the microcontroller and the selection of the A/D converter.