Abstract: This paper analyzes the Ethernet connection scheme based on a microcontroller, introduces the characteristics of the MC9S12NE64 16-bit microcontroller and its minimum system hardware design, and presents the initialization process, main program, and TCP/IP protocol stack implementation ideas of the MC9S12NE64. Keywords: MC9S12NE64; microcontroller; embedded system; Ethernet; TCP/IP 1 Introduction With the emergence of the Internet and the rapid development of Ethernet, Ethernet-based device control is becoming increasingly common and is developing rapidly. Currently, Ethernet (EtImmet) is widely used in various computer networks. Through Ethernet and the TCP/IP protocol stack, different network devices can interconnect and exchange data. There are various schemes for implementing network connections in embedded systems using Ethernet. The traditional multi-device Ethernet connection scheme is implemented by expanding the Ethernet controller through the MCU, and external RAM and ROM are also needed when necessary. Although this scheme is not difficult to apply, it uses a large number of external components, resulting in high system overhead and low stability. To address the shortcomings of traditional solutions, this paper discusses implementing single-device Ethernet connectivity using the MC9S12NE64, a 16-bit microcontroller integrating the Ethernet MAC and physical layers. Compared to multi-device solutions, single-device connectivity offers advantages such as fewer external components, lower system overhead, higher stability, and shorter design time. 2. Introduction to MC9S12NE64 The MC9S12NE64 is a 16-bit microcontroller based on the HCS12 CPU core manufactured by Freescale. It can be used to easily implement single-device Ethernet connectivity, forming a complete terminal node. The internal functional block diagram of the MC9S12NE64 is shown in Figure 1. Its main features are as follows: It employs a high-performance 16-bit HCS12 CPU core, operating at 25MHz or 10MIPS at 3.3V, and features an optimized C language architecture that generates very concise code. It has an on-chip debug interface for real-time online simulation and debugging without the need for an emulator. It integrates 64KB of nash memory and 8KB of static RAM, sufficient for most applications. External expansion is also possible if needed. This device integrates a 10/100Mbps Ethernet Media Access Controller (EMAC) with a built-in standard Media Independent Interface (MII) for address identification and filtering, Ethernet type filtering, and supports half-duplex and full-duplex communication. It shares a configurable EMAC buffer with 8KB of RAM, including one transmit buffer and two receive buffers. The MC9S12NE64's RAM operates at twice the speed of the CPU, allowing the CPU and EMAC buffers to access data interchangeably. It also integrates a 10/100Mbps Ethernet Physical Layer (EPHY), supporting auto-negotiation mode and half-duplex and full-duplex communication. It features self-diagnostic capabilities. It includes an 8-channel 10-bit analog-to-digital converter (fADC), 4-channel 16-bit timers, 2 Serial Communication Interfaces (SCI), 1 High-Speed ​​Serial Peripheral Interface (SPI), and 1 I2C interface with 256 clock speed options. It also features a clock and reset generator (CRG) module using a phase-locked loop and up to 70 general-purpose I/O ports. It is available in 80-pin TQFP-EP and 112-pin LQFP packages. 3. Simple Applications of MC9S12NE64 3.1 Hardware Design The MC9S12NE64 can be used to construct network terminal nodes with different functions, such as network servers, devices with Internet functionality, remote monitoring (data acquisition, diagnostics), remote control of field devices, and remote devices sending messages via email or text pagers. The hardware circuit schematic of a system based on the MC9S12NE64 with minimal peripheral components is shown in Figure 2. This minimum system consists of an 80-pin MC9S12NE64 and peripheral components. The circuit includes a background debugging connector J1; five LED status indicators (used to display network connection status, including EPHY conflict status, connection establishment status, data reception status, connection speed, and duplex mode); a necessary bias resistor R5; and a high-speed LAN electromagnetic isolation module (i.e., an RJ45 Ethernet interface). PHY_TXP and PHY_TXN are transmit lines, and PHY_RXP and PGY_RXN are receive lines. During the design process, the physical ports of the MC9S12NE64 must comply with the IEEE 802.3 physical layer specifications when connected to the isolation transformer. For example, the distance between the RJ45 jack and the isolation transformer should be minimized, and the traces for output and input differential signal pairs should be well isolated to ensure the rated load current of the power supply is not less than 300mA. The system clock requirements should also be considered during the design; the MC9S12NE64 only supports Pierce-type oscillators, and the crystal oscillator accuracy should be higher than 25ppm. In the system, the MC9S12NE64 operates in normal single-chip mode, and its internal regulated power supply is active. 3.2 MC9S12NE64 Initialization Before the MC9S12NE64 microcontroller begins operation, necessary initialization must be performed. This mainly includes the clock and reset generator (CRG) module, the EMAC module, and the EPHY module. Although the EMAC and EPHY on the MC9S12NE64 are designed as two independent modules, if the internal EPHY is used, both EMAC and EPHY must be initialized simultaneously. The initialization process of MC9S12NE64 is as follows: (1) Initialize the clock and reset generator module to generate a 25MHz internal bus clock. This process is accomplished by setting the register table of the clock and reset generator (CRG) module. (2) Set the DIS10 and DIS100 bits of the EPHYCTL0 register to 1 to disable the EPHY clock until EMAC and EPHY are configured. (3) Configure the EPHY address requested by MII through the EPHYADD0, E-PHYADD1, EPHYADD2, EPHYADD3, and EPHYADD4 bits of the EPHYCTL1 register. (4) Configure the auto-negotiation mode. Set the ANDIS bit of the EPHYCTL0 register to 0 to use the auto-negotiation mode. (5) Set the LEDEN bit of the EPHYCTL0 register to 1 to enable the EPHY to drive the LED signal. Set the EPHYIEN bit of the EPHYCTL0 register to 1 to enable the EPHY interrupt. Set the EPHYEN bit of the EPHYCTL0 register to 1 to enable EPHY to work, thus enabling Media Independent Interface (MII) operation between EMAC and EPHY. (6) Set the MDCSEL bit of the MCMST register to 0xA to configure the EMAC management data clock (EMACMDC). (7) Set the BUFMAP bit of the BUFCFG register to configure the size of the EMAC Ethernet buffer. The value of BUFMAP is used to determine the ratio of user RAM and EMAC buffer in the system RAM. The maximum value of BUFMAP is 4, at which point the size of a single buffer is 1.5K bytes, which is just enough to store a maximum Ethernet frame. Data packets larger than the buffer size will be filtered out, and should be selected reasonably during design. Set the MAXFL bit of the BUFCFG register to specify the maximum frame length to be accepted, so that the buffer plays the role of data filtering. (8) Configure the 6-byte MAC address through the MACAD register. If the device is not connected to the Internet, the MAC address can be defined by the user. (9) Set the ETCTL register to 0x17 to control the data types transmitted on the network. (10) Configure the EMAC MAC address filtering mode by setting the PROM, CON-MC, and BCREJ bits of the RXCTL register. If it is not in auto-negotiation mode, the RFCE bit also needs to be set to implement receive flow control. (11) Set the NETCTL register to 0x81 to configure the EMAC operating mode and enable the EMAC to work normally. (12) Set the IMASK register to configure the allowed EMAC interrupt signals. If a certain interrupt request signal needs to be enabled, set the corresponding bit to 1. (13) Set the PTRC bit of the TXCTS register and set the PTI-ME register to initialize and pass the pause duration. (14) Set the system interrupt to enable system interrupts. (15) Configure the EPHY through the EMAC MII management interface, including setting the speed, duplex mode, and flow control, and configure the EPHY interrupt control register to configure EPHY interrupt control. (16) In auto-negotiation mode, start the EPHY clock generator by setting the DIS10 and DIS100 bits of the EPHYCTL0 register to 0. After auto-negotiation is complete and the connection is established, the negotiation provisional and duplex settings are determined by the EPHY MII register. The EMAC must update the negotiation provisional and duplex settings using the configuration set by the FRCE bit of the RXCTS register and the FDX bit of NETCTL. At this point, the MC9S12NE64 initialization is complete, and data reception and transmission between the EMAC and EPHY can be performed. To enable communication between the system and other devices on the Ethernet (such as a PC), only the TCP/IP protocol stack needs to be implemented. Due to the limited internal resources of the microcontroller, it is difficult to support a complete TCP/IP protocol stack. Therefore, a specific TCP/IP protocol stack is set according to the characteristics and functions of each system, implementing only the protocols relevant to the needs, such as ARP, IP, ICMP, TCP, UDP, SMTP, and HTTPS. After system initialization, the main program loop begins, including the microcontroller's control functions and network data transmission. For the Ethernet transmission part, there are two main functions: first, to encapsulate and send the data to be sent according to the Ethernet data frame format; second, to unpack the received Ethernet data frames for use by the application. The main program implements Ethernet communication for the microcontroller by embedding the TCP/IP protocol. 4. Conclusion This paper implements embedded Ethernet communication based on the TCP/IP protocol using the MC9S12NE64 16-bit microcontroller. With the rapid development of digital and intelligent instruments, the application of Ethernet communication will become increasingly widespread. The MC9S12NE64 has built-in Ethernet MAC and physical layers, which can be used to easily implement single-circuit Ethernet connections. It is suitable for industrial control, security systems, user card meters, commercial automation, building control, lighting management, medical testing, vending machine environmental monitoring, sales equipment terminals, and home automation, etc.