PID controllers are widely used in CNC (Computer Numerical Control) machining, laser cutting, automated grinding roller arc welding systems, stepper/servo motor control, and other motor-controlled mechanical assembly positioning motion control systems. Their design technology is mature, with a long-established typical structure, convenient parameter tuning, and flexible structural modifications, meeting general control requirements.
In this type of motion control system, the controlled variable is often an analog quantity such as speed or angle. The error between the controlled variable and the set value is discretized and then calculated by the control algorithm implemented by the digital PID controller. Finally, it is converted into an analog quantity and fed back to the controlled object. This is the approximate approximation principle commonly used in PID control.
The performance of the control system with this structure design can only be close to the performance of the original continuous control system and will not exceed it. The accuracy of the approximation is related to the size of the transformed continuous mathematical model and the length of the sampling period [1]. Especially in the case of high-speed motion control, the influence of the sampling period is greater. The approximation is better when the sampling period is relatively long, but it also puts forward higher requirements on the calculation speed of the PID control algorithm and the adjustment time of the loop.
Programmable logic devices (FPGAs) have 5,000 to 2 million logic gates, classifying them as large-scale or even very large-scale logic devices, with operating frequencies up to 250MHz. Therefore, they are perfectly suited for implementing high-speed PID controllers, both in terms of programming scale and operating speed. This design uses Altera's Cyclone series FPGA device EP1C3 as the hardware development platform to optimize the incremental digital PID control algorithm commonly used in motion control, improving computational speed and loop settling time.
1. FPGA Implementation of Incremental Digital PID Control Algorithm
The classic PID control equation is:
In the formula, KP is the proportional gain; K1 is the integral time constant; and KD is the derivative time constant. The implementation of a digital PID control algorithm must employ numerical approximation. When the sampling period is quite short, summation replaces integration, and difference quotients replace derivatives, thus discretizing the PID algorithm. After discretizing, differencing, and merging the differential equations describing the continuous-time PID algorithm, we obtain:
As can be seen from equation (2), the incremental digital PID algorithm only needs to store the three most recent error sampling values e(k), e(k-1), and e(k-2). The structure diagram of this incremental digital PID control algorithm is shown in Figure 1.
The structure within the dashed box in Figure 1 consists of three multipliers with shift functionality, which can be implemented using the rigorously tested and optimized macro function modules LPM_MULT (M0～M2) provided by Altera. LPM_MULT is a customizable bit-width adder/multiplier. Here, the custom error input value e(k) has a bit width of 8 bits, and the other constant multipliers q0, q1, and q2 are the control parameters of the tuned PID controller, with a bit width of 6 bits. The multiplier output has a bit width of 14 bits. The schematic diagram in Quartus II is shown in Figure 2.
The LPM_MULT macro module can also customize the number of synchronization pulses (clock) waited for when outputting the operation result; this is the pipelined output function of LPM_MULT. Figure 2 specifies that the wait times for lpm_mult0, lpm_mult1, and lpm_mult2 are 1, 2, and 3 synchronization pulses respectively. This design naturally implements the shift multiplication operation; at the same time, the pipelined function of the multiplier improves the speed of the multiplication operation. The optimized functional simulation waveform is shown in Figure 3.
As shown in Figures 2 and 3, at the rising edge of the Kth pipeline advance clock signal clk, lpm_mult0 outputs the product result step1out at the current time, lpm_mult1 outputs the product result step2out at time K-1, and lpm_mult2 outputs the product result step3out at time K-2. The output value of the parallel addition unit parallel_add is result = step1out + step2out + step3out.
2. Design and Simulation of General-Purpose Analog-to-Digital and Digital-to-Analog Converters
In order to maintain the versatility and scalability of the system, the typical_ADC component of the general A/D conversion was designed to realize the analog-to-digital conversion simulation function of the system, referring to the timing diagram of the AD7822, an 8-bit, semi-flickering A/D converter of ADI. The typical_ADC component is an idealized A/D conversion chip, mainly composed of an 8-bit address counter and a ROM for storing sine data. It simulates the sampling and quantization process of sine signals, and the sampling period is only related to the working clock of the system [2].
Compared to analog-to-digital (A/D) conversion, digital-to-analog (D/A) conversion requires fewer control signals and has simpler timing requirements. Referring to the function table of TI's 14-bit D/A converter chip DAC8806, a general-purpose D/A converter, typical_dac, was designed to implement the system's D/A conversion simulation function. To formally represent the system's D/A conversion process, typical_dac simply performs a parity check operation on the PID algorithm's output Δu(k), described in VHDL as follows:
The architecture of typical DAC is based on the following: when the conversion control signal wr is low, the output outputs the XOR value of each bit; otherwise, the output is in a high-impedance state.
uout<=(datain(0)XOR datain(1)XOR datain(2)XOR datain(3)XOR datain(4)XOR datain(5)XORdatain(6) (13)XOR｀1｀)WHEN wr=｀0｀ELSE｀z｀;END behav;
3. Design of the working control state machine
A typical digital PID control system consists of three key components: A/D conversion, PID control algorithm, and D/A conversion. To coordinate the workflow between these three components, a system control unit is essential. There are various options for sequential control in purely hardware digital systems, such as microcontroller-assisted control, embedded CPU soft-core control, and pulse counting control, but none of these can simultaneously achieve high-speed control and flexible expansion. In terms of high-speed computation and control, finite state machines offer advantages that are difficult for the aforementioned control methods to surpass.
Based on the signal output method of the state machine, there are two types of state machines: Moore type and Mealy type. From the perspective of output timing, the former belongs to synchronous output state machine, while the latter belongs to asynchronous output state machine. The output of the Mealy type state machine is a function of the current state and all input signals. Its output occurs immediately after the input changes and does not depend on clock synchronization [2].
Moore-type state machines output only as a function of the current state. When the input changes, they must wait for a clock cycle; the output only changes when the clock cycles change the state. Therefore, they wait one more clock cycle than Mealy machines, but effectively avoid glitches. The state machine used in this design is a single-process Moore-type state machine. The state transitions are shown in Figure 4.
4 System Implementation and Functional Simulation
The entire PID controller system design adopts a top-down design method and a modular design concept. That is, the VHDL system behavior description is first obtained from the natural language description of the PTD controller, and then the system is decomposed into four main modules: error A/D conversion unit, PID calculation unit, control increment D/A conversion, and control state machine that coordinates the three.
Altera's proprietary EDA software, Quartus II, supports a mixed input design approach using schematics and VHDL. Except for the PID controller, which uses schematic input, the other three components use VHDL input. During system simulation, if the system's maximum operating speed is set to 120MHz, the sampling rate is 24MHz. The functional simulation waveform is shown in Figure 5.
Optimization of the incremental digital PID control algorithm significantly improved the system's operating speed. Simulation results show that the low conversion rate of the A/D converter is a bottleneck in improving the system's operating speed. For the flashing A/D device used in this design, reducing the time the state machine waits for the A/D conversion completion signal EOC (see Figure 4), i.e., increasing the A/D conversion rate, is key to improving the overall system operating speed.
The incremental digital PID control algorithm used in this design can be applied to FPGA designs of finite impulse response (FIR) and infinite impulse response (IIR) filters, and pipeline optimization techniques can also be used to improve operating speed. Furthermore, due to the versatility of PLD design and dedicated ASIC design, designs completed on the PLD design platform can be seamlessly transitioned to dedicated ASIC design, further enhancing system reliability and integration.
