Abstract: This paper introduces the features of the TM1300 DSP and presents a design method for implementing an Ethernet communication interface by driving an Ethernet chip through the TM1300's PCI interface. This design combines the TM1300 with Ethernet, thus facilitating video communication. The paper details the key design points of the software and hardware of this scheme and finally presents experimental results for transmitting analog data and actual video compressed bitstreams. Keywords: PCI bus, TM1300, Ethernet communication interface, pSOS+ core, pNA+ 1 Overview The TM1300 is a new generation of high-performance multimedia digital signal processor chip launched by Philips. DSP application systems based on the TM1300 are suitable for real-time audio and image processing and can be widely used in applications such as video conferencing, videophones, and digital television. It not only has powerful processing capabilities but also features very user-friendly audio and video interfaces, as well as I/O interfaces such as SSI and PCI, allowing for flexible construction of various video communication systems according to application needs. Given the current popularity of computer networks and the development of online video services, it is necessary to develop an Ethernet interface for the TM1300 video encoding system to broaden its application scope. A reasonable approach to developing an Ethernet interface is to utilize the PCI interface integrated into the TM1300 to drive a dedicated Ethernet interface chip. Since most Ethernet interface chips (such as Real-tek 8029, Realtek 8139, etc.) currently use PCI interfaces, data can be transferred from the TM1300 to these dedicated Ethernet interface chips via the PCI bus, and then they can send the data. Furthermore, the TM1300 can run in the embedded operating system pSOS, and since the pSOS system includes a TCP/IP protocol stack, TCP/IP encapsulation of the encoded data stream can be easily performed. Based on this approach, the author designed the circuit board after preliminary testing and successfully completed debugging. Currently, this Ethernet interface has been basically successfully developed. This article will provide a detailed introduction to the key technical points of this design from both hardware and software perspectives. 2 TM1300 and PCI Bus Interface The hardware structure block diagram of this system is shown in Figure 1. The focus of the hardware design of this system is the PCI bus interface. PCI buses are available in 32-bit and 64-bit versions based on their data bit width; the 64-bit data lines are compatible with the 32-bit version. The 32-bit PCI bus is common in PCs, with a total of 110 useful pins, which can be divided into three groups. The first group consists of basic function signal lines, including the 32-bit shared data address lines AD[00..31], interface control lines, arbitration lines, clock lines, system reset lines, and interrupt lines. The second group consists of additional function signal lines, including error reporting lines, cache support lines, and JTAG boundary scan lines. The third group consists of power lines, including device power consumption indicators, 3.3V power lines (12 pins), 5V power lines (13 pins), and ground lines (22 pins). Because the Realtek 8029 does not have the cache and JTAG boundary scan functions supported by the additional function signal lines of PCI, and although it has a parity error reporting pin, this pin can be left floating, the design only needs to consider the connection of the first group of function signal lines. The design of the PCI interface has the following key points: (1) Arbitration of the PCI bus. Here, we need to explain two concepts. First, the PCI bus is shared by multiple devices. Since there can be multiple PCI devices in a PC, an arbiter is needed. Second, PCI devices are divided into master devices and slave devices. The master device can initiate the transmission of PCI data, while the slave device can only passively respond to the operation of the master device to respond to read and write operations. The arbitration pins of PCI are REQ and GNT, which are the request line and the authorization line, respectively. Only the PCI master device has these two pins. In general, REQ and GNT are usually connected to the arbiter in pairs, while the REQ and GNT of devices are usually not connected to each other. The arbitration process of the PCI bus is as follows: The PCI master device pulls the REQ level low to indicate that it requests the arbiter to occupy the bus. After the arbitration is approved, the arbiter pulls the GNT level of the device low to indicate that the request is approved. After that, the device can use the bus. When it no longer uses the bus, the REQ signal should be made high, and the arbiter will no longer allocate bus resources to it. In this system, the TM1300 is the PCI master device, and the Realtek 8029 is the PCI slave device. Since they do not have a shared bus issue, no arbiter is needed. Simply shorting REQ and GNT is sufficient, which is equivalent to the TM1300 authorizing itself. (2) The role of the PCI_IDSEL signal line in the PCI configuration read and write of the device PCI has a special read and write cycle called configuration read and write. This is because if the device is not configured with I/O or memory address during system boot, the software can only access the device by configuration. There are two types of configuration read and write, called type 0 and type 1 respectively. Which one is used depends on the hardware connection of the bus. When the configuration read and write operation does not go through the PCI bridge, type 0 is used. When it needs to go through the PCI bridge, type 1 is used. The address of type 0 read and write is directly the address on the bus. The address of type 1 read and write needs to be decoded by the PCI bridge to become the final bus address. In this design, the TM1300 and Realtek8029 are directly connected via the PCI bus, so type 0 configuration is used for read and write. AD [00..31] are the shared address and data lines of the PCI bus, and each PCI transfer is divided into an address cycle and a data cycle. During the address cycle, when using type 0 read/write, the contents of AD[00..31] are as follows: AD[00] and AD[01] are always "00" because configuration read/write is done in double-word units. AD[02] to AD[07] are the register numbers of the PCI configuration space to be read/written; AD[08] to AD[10] are the function numbers of the device. When there are multiple functional devices on a PCI card, these bits are used to further distinguish different devices. Since the Realtek 8029 is a single-function device, these bits are all 0. AD[11] to AD[31] are device select bits, of which one and only one bit must be "1", as shown in Figure 2. This is physically manifested as one of the AD[11] to AD[31] lines on the bus being high. If the line outputting the high level is connected to the PCI of a certain PCI card... When the IDSEL pin is connected, the card will be activated. In the following data cycle, it will put the contents of the corresponding register in its PCI configuration space onto the bus for reading. (3) Processing of PCI_FRAME, PCI_DEVSEL, PCI_IRDY, and PCI_TRDY pins. All four pins are active low, so pull-up resistors are required to ensure that the pin is in a stable inactive state when the device does not drive it. The resistance value of the pull-up resistor is in the range of 1kΩ to 10kΩ. The smaller the resistance value, the shorter the time for the signal to be driven into an active state. However, if the resistance value is too small, it will lead to excessive current. Therefore, a balance must be struck. In this design, 4.7kΩ is selected. The above three points have general reference significance for the interconnection of PCI devices in offline conditions. In addition, this design has the following unique points: ● The PCI and INTA pins of the TM1300 should be configured as inputs to receive interrupts from the Realtek 8029; ● The PCI clock is provided by the TM1300; ● The reset signal of the Realtek 8029 is also the reset signal of the TM1300, and this signal is provided by external circuitry; ● The PCI STOP and PCI SERR pins of the TM1300 are left floating, indicating that the Realtek 8029 does not have the corresponding additional functions. Furthermore, the PCI INTB, PCI INTC, and PCI INTD pins of the TM1300 can be used as user interrupts. 3 Software Design The software structure block diagram of this interface design is shown in Figure 3. The TM1300 runs on pSOS, a simple real-time multitasking embedded operating system with a pNA+ network component. pNA+ is essentially an extension of the TCP/IP protocol stack, providing an application programming socket interface at the top and defining an interface for interaction with the network interface layer at the bottom. This interface includes eight functions: ni_init (interface chip initialization), ni_broadcast (send broadcast packets), ni_send (send normal packets), ni_getpkb (request send buffer), ni_retpkb (return receive buffer), ni_ioctl (I/O control operation), ni_pool (statistics query), and Announce (called by the network interface driver to submit received packets to pSOS). In this application, the network interface layer is the Realtek 8029 driver, which drives the Realtek 8029 through a hardware abstraction layer (Hardware Abstraction Layer is the collective term for the PCI bus configuration read/write and I/O read/write instruction set). The software execution flow is roughly as follows: The system first starts pSOS, which loads the network interface driver and then calls the driver's `ni_init` function. Simultaneously, it initializes the Realtek 8029's PCI configuration space and sets the Realtek 8029's operating parameters. Afterward, the user task is started. Here, the user task is the H.263 encoding process. It compresses and encodes the source image read from port VI, then calls the socket's interface function `sendto` (a dedicated UDP socket send function), and sends the bitstream to pSOS. pSOS encapsulates the data according to the UDP protocol and then calls the `ni_send` function. `ni_send` copies the data packet from the system's main memory to the Realtek 8029's on-chip RAM, and then the Realtek 8029 starts sending data. In the receiving case, after the Realtek 8029 receives a complete data packet, it notifies the CPU via an interrupt, and the CPU then executes the interrupt service routine. After the interrupt service routine copies the data packet from the Realtek 8029's on-chip RAM to the system's main memory, the system calls the Announce function and submits the data block pointer, data length, and other information to pSOS. Finally, pSOS uploads the data packet layer by layer along the protocol stack and performs corresponding processing. The software design is closely related to the pSOS operating system; due to space limitations, this article will not go into detail about pSOS. This article will focus on the configuration process of the PCI configuration space, which has general reference value for similar designs. The PCI configuration space is 64 bytes. These registers on the PCI chip store important codes such as the chip's vendor code, device code, and device type, as well as registers that control its bus behavior, such as the command register and base address register. These must be correctly configured during device initialization; otherwise, the device will not function. Configuring the Realtek 8029 PCI space requires three steps: First, scan the bus. The purpose of this step is to find the configuration address of the Realtek 8029. Intuitively, this means finding which AD line is connected to its PCI_IDSEL pin, as subsequent configuration writes will rely on this address for addressing. During the bus scan, each line from AD[11] to AD[31] should be scanned once. If any AD line is connected to the PCI IDSEL pin of a PCI device, then reading register 0 of the PCI configuration space using the configuration read function should return the device and vendor code of that device. If the line is not actually connected to a device, the return value is 0. The device and vendor code of the Realtek 8029 is known to be "0x802910ec". If the return value matches this, it means the Realtek 8029 has been found. At this point, the sequence number of this AD line should be noted. For example, if the PCI IDSEL and AD[20] of the Realtek8029 are connected in hardware, the scanned sequence number should be "20". Next, the I/O read/write enable is configured using the configuration write function, i.e., "0x1" is written to the command register. Finally, the I/O address is configured using the configuration write function, i.e., the I/O address assigned to the device (e.g., "0xe400") is written to the I/OBaseAddress register. The specific program flowchart is shown in Figure 4. 4. Debugging Results Based on the above design, the author added a PCI interface to the original TM1300 video encoding hardware system and wrote a driver program for the Realtek8029 under pSOS. Then, data transmission tests were conducted on the Realtek8029 driver on this hardware platform. The author first used a separate UDP sending task to test the sending rate. This task mainly involved sending data packets at high speed to a PC on the network; the size of the data packets was variable. The results of the PC receiving and counting the number of lost packets are shown in Table 1. Experiments showed no errors under various test rates when directly connected via Ethernet cable. However, when connected to a local area network (LAN), a small number of sudden errors occurred at a transmission rate of 4.5 Mbps. Since UDP is an unreliable transmission method, these errors are normal. During testing, the highest UDP transmission rate reached approximately 5 Mbps, which is still somewhat lower than the hardware's maximum rate (10 Mbps). This is mainly because the data copying process from the system's main memory to the Realtek 8029's on-chip RAM does not currently use DMA, which is an area for improvement. Table 1 shows the packet loss statistics (unit: number of lost packets/minute). Next, the author conducted a joint test of encoding and transmission. After H.263 data compression, the encoding task sent the bitstream from the Ethernet interface, which was then received and decoded on another PC on the network. The output bitrate can be controlled by adjusting the encoder's quantization step size. In the experimental environment, it was found that when the quantization step size was greater than or equal to 5 and the bit rate was below 700kbps, there was basically no packet loss, and the decoded image was relatively stable. However, when the quantization step size decreased further and the bit rate approached 1Mbps, packet loss occurred, and colored squares appeared in the decoded image. This phenomenon occurs because the H.263 encoder consumes a lot of CPU resources, and the copying of data between main memory and Realtek 8029 on-chip RAM using I/O read/write also requires a certain amount of CPU resources. Thus, when the quantization step size is less than 5, the processing complexity exceeds the CPU's capacity, resulting in some bit errors. Solutions include improving the data transmission method (using DMA) and optimizing the encoding task. 5. Summary This paper introduces the design of the PCI bus interface and the steps of PCI space initialization, and provides a detailed analysis of the test results, proposing directions for future improvement.