0 Introduction A typical underwater image transmission system uses a DSP (Digital Signal Processor) as the core unit for real-time image processing and a PC to establish a user-friendly human-machine interface for image acquisition and display. Therefore, efficient and fast data transmission is required between the PC and the DSP. Currently, the PC and DSP often use RS-232 serial communication for data exchange. While the communication protocol is simple, it is difficult to meet the real-time requirements of transmitting large amounts of image information. Furthermore, the PC's serial port resources are very limited. USB (Universal Serial Bus), as a fast and flexible new interface, can meet the requirements of real-time exchange of large amounts of data in most cases. This paper proposes an image transmission system scheme based on a USB interface, introduces the USB interface design between the DSP and the host computer, and utilizes TI's TMS320VC5502 DSP chip and Cypress's Ez-USB SX series chip CY7C68001 to complete the hardware and software design for USB interface expansion, achieving high-speed data transmission between the DSP and the host computer. 1 System Overall Scheme The overall system structure is shown in Figure 1. At the transmitting end, the PC converts the image to be transmitted into a data bitstream and sends it to the USB bus. Simultaneously, the original image is displayed on the host screen. The image data is processed by the DSP and peripheral circuits before being sent to the channel. The receiver processes the received signal and then transmits the image data back to the host computer via the USB bus, displaying the received image. The design of the USB interface between the DSP and the host computer is the focus of this paper. 2 Hardware Design The hardware design for the USB interface expansion is shown in Figure 2. The TMS320VC5502 is a fixed-point 16-bit chip. As the most cost-effective new product on the TI TMS320C5000 DSP platform, it boasts a processing speed of up to 60 billion multiply-accumulate operations per second. It features one 32-bit program read bus and five 16-bit data buses. It integrates on-chip ROM (16 k × 16 bit), DARAM (32 k × 16 bit), and other memories, along with abundant peripheral resources, meeting the requirements for large-scale image processing. Furthermore, the chip's low power consumption (less than 200 mW) allows it to be applied to underwater image transmission systems. Due to the limited I/O port resources of the DSP, the system uses the FPGA chip EPF10k10A for address decoding. It has 66 user I/O ports. Some address lines of the DSP are connected to the FPGA's I/O ports and configured as input ports. By simulating the decoder logic through the FPGA program, chip select signals for all modules communicating with the DSP, such as Flash memory, SDRAM, USB, and UART, can be generated, thus expanding the DSP's I/O ports. The USB communication protocol is relatively complex; therefore, this system uses the Cypress CY7C68001 chip to implement the USB 2.0 interface. This chip integrates a USB 2.0 transceiver and a SIE (Serial Interface Engine), handling data communication management at the physical layer and data link layer, respectively. The USB application layer protocol is implemented using a TMS320VC5502. The CY7C68001 chip supports high-speed (480 Mbit/s) or full-speed (12 Mbit/s) USB data transfer; it has four internal endpoints sharing a 4 kB FIFO, and the FIFO space size and FIFO state of each endpoint are programmable; the chip also has a smart SIE function, which can complete enumeration without the aid of microprocessor interrupts. The CY7C68001 has 16 data bus FD[15:0] and 3 address lines FIFOADR[2:0] for selecting the command interface or a specified FIFO. In addition, the /INT signal indicates that an interrupt event has occurred in the CY7C68001, or notifies the DSP that the read operation on the CY7C68001 has ended; the READY signal indicates that the CY7C68001 is in a read/write state. 3 Software Programming 3.1 Host Program The USB protocol includes four basic data transfer types: control, isochronous, interrupt, and bulk. Batch transmission is particularly suitable for transmitting large amounts of data, ensuring fast and accurate transmission when there are no bandwidth or interval requirements. Therefore, this system uses batch transmission for image data transmission between the PC and the DSP. The host software consists of three parts: a) The CY7C68001 driver, used to discover, configure, and disable USB devices, and to implement data transmission interfaces and control functions. Combined with the EZ-USB GPD (Generic Device Driver), the system file (.sys) of the driver is compiled and generated in the Windows WDM DDK environment. b) The USB installation information file (.inf), used to bind the driver to the specific device's Verdor ID (VID) and Product ID (PID). When a USB device is plugged into the computer, the computer detects the insertion and automatically sends a query request; the USB device responds to the request and sends its VID/PID. The computer loads the corresponding device driver based on these two IDs to complete the enumeration. c) The system's host computer (PC) processing program, written in Microsoft Visual C++, generates messages through operations on controls on the interface, causing the CPU to execute corresponding actions. Taking the sending end as an example, the host program flow is shown in Figure 3. The interface functions between the driver and the application are defined as follows: [align=left] For the user, all applications access the EZ-USB GPD through IO control. The above interface functions mainly call two Win32 API functions: First, connect to the USB device through CreatFile() and obtain the handle to access the device driver; then call DeviceIoControl() to submit the I/O control code (IOCTL), send the corresponding command to the driver, and set the I/O buffer for the device handle returned by CreatFile(). Partial source code is as follows: [/align] 3.2 DSP-side program Data transmission between the USB host and the device is carried out through endpoints in the device. These endpoints are identified by endpoint number and input/output direction, and a fixed FIFO storage area is allocated for data transmission. During initialization, the four endpoints of CY7C68001 are configured for bulk transmission. Among them, FIF02 and FIF04 are output endpoints used to receive data from the host computer; FIF06 and FIF08 are input endpoints used to store data to be sent. Each FIFO is set to asynchronous working mode. After initialization, the DSP enables the USB external interrupt, writes the descriptor table to the CY7C68001, and waits for its enumeration interrupt. Upon successful enumeration, the DSP performs other configurations on the CY7C68001 and clears the FIFO, then waits for the host to send a user request and processes it accordingly. The program flow is shown in Figure 4. The program was compiled and debugged successfully in the TI CCS 2.2 integrated development environment. 3.2.1 USB Initialization Each USB device has an internal device descriptor table containing all the device's requirements and characteristics. The process of identifying and configuring a newly connected USB device through control transmission between the host and the device is called device enumeration. The CY7C68001 chip has a 500-byte descriptor RAM to store the descriptor table, and the internal DESC register stores the length of the descriptor table. The CY7C68001 enumeration method has two modes: EEPROM bootstrapping and DSP bootstrapping (default). This system uses the default method: first, the DSP writes a 2-byte descriptor table length to the DESC register, and then writes the descriptor table byte-by-byte to the descriptor RAM via the command port. After the descriptor table is written, the DSP waits for a successful enumeration interrupt from the CY7C68001. After successful enumeration, the CY7C68001 completes the configuration of each endpoint. 3.2.2 Register Reading and Writing of CY7C68001 The DSP uses a two-stage addressing method to read and write to the CY7C68001 registers. That is, first, the sub-address of the register to be addressed and the operation type (read/write) are written via the command port, and then the data is read or written via the command port. For specific steps, please refer to the CY7C68001 chip datasheet. 3.2.3 The CY7C68001's SX2 interrupt has the following six interrupt sources: SETUP: SX2 receives a host computer request that cannot be automatically processed; EPOBUF: The buffer of endpoint 0 is in a readable/write state; FLAGS: The OUT endpoint FIFO becomes non-empty; ENUMOK: SX2 enumeration succeeds; BUSACTIVITY: Bus suspend/resume; READY: Wake-up from low power via the WAKEUP pin. When an interrupt event occurs, the CY7C68001 triggers a DSP interrupt via the INT signal. The DSP determines the interrupt source by reading the command port in the USB ISR (Interrupt Service Routine) and sets the corresponding interrupt flag. If it is a SETUP interrupt, i.e., SX2 receives a user request that cannot be automatically processed (such as a user-defined batch read/write), then in the subsequent interrupt handling, the ISR reads 8 bytes sequentially from the command port, stores them in the user command buffer, and then the main program parses and executes them. 4. Conclusion This system utilizes the USB 2.0 interface chip CY7C68001 to achieve high-speed image data transmission between the host computer and the DSP, establishing a good human-machine interface for the underwater image transmission system. Users can send the images to be transmitted to the transmitter's DSP using a PC, and the receiver's DSP will send the received image data back to the PC for display. Users can intuitively compare the transmitted and received images.