In 2002, Invensys (UK), Mitsubishi Electric (Japan), and Motorola (USA) announced the formation of the ZigBee Technology Consortium to jointly research ZigBee technology. In 2003, IEEE also developed the IEEE 802.15.4-2003 wireless specification for LR-WPAN (Low-Rate Wireless Personal Area Networks), defining a new physical and MAC layer for wireless devices. It aimed to develop a low-cost, low-power, and low-data-rate wireless connectivity technology applicable to fixed, portable, or mobile devices, with the goal of automated control. It employed DSSS spread spectrum technology, with an effective coverage range of 0–300 m depending on the data rate. The IEEE 802.15.4-2003 protocol specified 27 communication channels: one at 868 MHz with a rate of 20 kbps; ten at 915 MHz with a rate of 40 kbps; and sixteen at 2.45 GHz with a rate of 250 kHz. Supporting three topologies—star, tree, and mesh—the network is functionally divided into two types of devices: Full Functional (FFD) and Reduced Functional (RFD). To simplify the protocol, IEEE 802.15.4-2003 conforms to the OSI reference model, defining the physical layer and MAC layer. Each layer completes its defined tasks and provides service task interfaces to the upper layers. Data communication in the protocol can be divided into direct data transmission and indirect data transmission, and is packaged and sent in the form of data frames. The network can operate in both superframe and non-superframe modes. To improve reliability, it employs the CSMA/CA media access control mechanism, acknowledgment frame response method, and CRC-16 ITU verification mechanism, and can add some data encryption and security control modes. For low power consumption and low cost considerations, the physical layer has only 14 service primitives, and the MAC layer has 35 primitives. Compared to Bluetooth, these primitives are only 1/3 of its number. 1 Hardware Circuit Design The basic structure of a typical IEEE 802.15.4 network device is shown in Figure 1. The system is typically powered by a battery, but can also be supplied by a voltage regulator module. The RF transceiver chip is responsible for generating, receiving, and demodulating radio frequency signals, with its reference clock provided by an external high-precision crystal oscillator. It also implements basic physical and MAC layer functions, such as encoding/decoding, channel selection, power control, receiver energy detection (RSSI), link quality indication (LQI), free channel assessment (CCA), and hardware CRC check. While achieving these basic functions, the RF chip should strive for low power consumption, high sensitivity, and a small package size. The microcontroller must have ample resources to control the RF chip and provide real-time responses to sensors, various application interfaces, and user interfaces. Typically, the protocol stack requires approximately 32 KB of storage space. 1.1 AT86RF230 Performance and Internal Structure Atmcl's AT86RF230 is a ZigBee/IEEE 802.15.4 compatible wireless RF transceiver chip. Operating in the 2.4 GHz ISM band, it boasts a 104 dB link budget, -101 dB receive sensitivity, and 3 dB transmit power, thereby reducing the total number of nodes required in the network and significantly lowering the networking cost of the IEEE 802.15.4 system. All key RF components (except the antenna, crystal oscillator, and decoupling capacitors) are integrated into a single chip, packaged in a 32-pin, 5 mm × 5 mm × 0.9 mm QFN package. Devices built from this chip require only six external components, as shown in Figure 2. The terminal node is typically battery powered, consuming 17 mA in transmit mode, 15 mA in receive mode, and only 0.7 μA in sleep mode; the operating voltage ranges from 1.8 to 3.6 V, and it includes an integrated 1.8 V LDO. The AT86RF230 has 35 8-bit registers accessible via SPI timing control, and operates in eight basic states (expandable to 14 as needed). The on-chip data transmission and reception buffers are 129 bytes and 130 bytes respectively, which perfectly meets the IEEE 802.15.4 protocol's requirement of a maximum frame length of 127 bytes. A 2-byte CRC16 checksum is added during transmission, and an additional 1-byte link quality indicator is added during reception. 1.2 Hardware Circuit Composition of the Network Device The schematic diagram of the main hardware components is shown in Figure 3. The module's digital interface consists of the SPI interface between the ATmega1281 and AT86RF230, along with four other control lines. The AT-mega1281 is an 8-bit high-performance AVR microcontroller from Atmel. Its basic features include: a RISC architecture, 135 instructions, and a throughput of up to 16 MIPS when operating at 16MHz; on-chip 128 KB Flash, 4 KB on-chip E2PROM, and 8 KB SRAM, allowing program download via ISP or JTAG; a maximum operating frequency of 16 MHz, an operating voltage of 1.8–5.5V, and a power-down current of only 0.1μA. In this design, the ATmegal281 operates at an internal 8 MHz oscillation frequency. If an external clock signal synchronized with the AT86RF230 is to be used, the CLKM pin should be connected to the XTAL1 pin of the ATmegal281, and the fuse bit should be set to external clock. The various operating state interrupt signals of the AT86RF230 are controlled by the IRQ pin, which is connected to the ICP1 pin of the ATmegal281 to generate a capture interrupt. Capture interrupts can be configured with noise cancellation to reduce external interference, thereby improving interrupt reliability. For details on the AT86RF230 register SPI read/write timing, state transition diagrams, and specific methods for various interrupt control, please refer to the references. It should also be noted that the long-term operating frequency stability of the external crystal oscillator X1 connected to the AT86RF230 must be less than or equal to 40 ppm, and an appropriate load capacitor should be selected based on the crystal oscillator and the chip's drive capability. For the analog section design, anti-interference measures are required to reduce interference from other parts and improve RF performance. For example, add a ferrite bead or inductor to the analog power input; separate the analog and digital grounds of the AT86RF230 and ground them at a single point; to reduce the influence of distributed parameters, the ground plane should be as large as possible and vias should be appropriately added; the capacitors used for filtering should also be placed as close to the chip as possible. Additionally, impedance matching is crucial. The AT86RF230 antenna port has two 100Ω differential outputs, which can be directly connected to differentially fed antennas, but the disadvantage is that impedance matching and testing are relatively difficult. Generally, a balun can be used to convert the two 100Ω differential outputs into one 50Ω output, which can then be connected to various single-ended fed antennas. When controlling the impedance of the PCB conductors at the RF signal output pin, the model shown in Figure 4 can be used. Based on the selected parameters, use the free software Ap-pCAD provided by Agilent Technologies, enter the Passive Circuits interface, and select the appropriate model. This design uses the Coplanar Waveguide model; after inputting the parameters, the characteristic impedance of the feed line can be calculated. If the actual test results show that the impedance of the feeder designed according to the calculation results does not reach 50Ω, 50Ω matching can be achieved by adding inductor L2 and corresponding capacitor C1 or C2. For antenna selection, either a 100Ω differential antenna or a 50Ω single-ended antenna can be used, as long as a balun for converting from dual-ended to single-ended is added as needed. Using a dipole board or F-type PCB antenna has the advantage of relatively high gain and strong anti-interference capability; a sheet antenna is small in size, but has low gain and is susceptible to interference. 2. Software Design The software development environment is AVRSTUDIO+AVRGCC. Both software programs are free. The software design mainly includes three parts: RF driver, peripheral circuit control, and ZigBee protocol stack design. The software flow of the coordinator and network nodes in a WPAN network based on the IEEE 802.15.4 protocol is basically the same, except that the network coordinator is responsible for network establishment, while the network nodes are responsible for some control or measurement functions. To ensure compatibility with other ZigBee products, the software design must strictly adhere to the IEEE 802.15.4 protocol. The network topology established in this design is a non-superframe star network, and the specific software flow is shown in Figure 5. The basic process is as follows: The network coordinator first initializes the WPAN information database, establishes the ZigBee network, assigns network IDs and 16-bit network addresses, initializes the neighbor device table, and then waits for other nodes to connect. After the network node powers on, it initializes its internal resources and the network node's WPAN information database, sends a scan signal to request a connection, and upon successful connection, records the network ID and the assigned 16-bit network address, and sends information to the coordinator according to its function settings. Because network nodes are generally battery-powered, they must enter a sleep-energy-saving state when idle. Peripheral circuit control mainly targets the control of sensors, switches, and other devices; the software can be modified accordingly based on different needs. 3. Test Results and Summary The performance evaluation of the ZigBee/IEEE 802.15.4 network equipment mainly tests its transmit power, spectrum phase noise, adjacent channel interference, and communication distance. Because the AT86RF230 lacks a pure carrier output mode, the output power and the frequency offset corresponding to the maximum gain point can only be analyzed by testing the modulation signal spectrum. Figure 6 shows the output spectrum of the modulation signal at 2.405 GHz for channel 11, from which the frequency point corresponding to the maximum power can be observed. In open-field testing, the bit error rate at a distance of 150 m is less than 1%. The system consumes 23.7 mA in transmit mode, 21.78 mA in receive mode, and only 2.5 μA in sleep mode. Experimental results demonstrate that the WPAN network device based on the AT86RF230 transceiver designed in this paper has the advantages of high fault tolerance, superior performance, ultra-low power consumption, and low cost, meeting the practical needs of various applications. Through continuous improvement of the hardware and software design, it is believed that the performance indicators of this system can be further enhanced.