Abstract: This paper analyzes the current update and design trend of 8-bit microcontrollers, mainly discusses the product design of its RISC architecture, and focuses on the key technologies used in the design from the perspective of architecture, in terms of high performance and low power consumption. Keywords: RISC; microcontroller; low power consumption; pipeline 1. Introduction Since the emergence of microcontrollers in the 1970s, they have developed rapidly and been widely used in nearly 30 years. With the rapid development of microelectronics technology, microcontrollers have been widely used in home appliances, computing and peripherals, communications, industrial control, automated production, intelligent equipment and instruments, etc., due to their outstanding advantages such as good performance, small size, low price and complete functions. They have become the most powerful tool for scientific research, teaching and industrial technology transformation. From the simple microcontrollers that initially adopted the Princeton structure to the RISC microcontrollers that now generally adopt the Harvard bus structure, microcontrollers have achieved rapid development [1]. 8-bit microcontrollers are currently the most widely used microcontrollers and the market that the most companies are currently focusing on. The market and price competition are extremely fierce, and the speed of new products with various multi-functional needs and different specifications is also extremely fast. With the rapid development of integrated circuit and semiconductor process technology, the continuous competition and integration of FPGA and SOC technologies, the design of electronic products is gradually moving towards better system performance, lower power consumption, lower cost, higher reliability, and easier development. Therefore, the rapid launch of high-performance, low-power, and high-economic-efficiency 8-bit microcontroller chips or IP Cores that meet market demands has become a hot topic of competition for many companies. 2. Current update and design trends of 8-bit microcontrollers For different microcontroller (MCU) product applications, it is necessary not only to consider the cost performance of MCUs from different manufacturers, but also to consider the application characteristics of MCUs under different instruction systems. In response to the continuous emergence of new intelligent electronic products, we have been developing new MCU products suitable for different embedded system applications [2]. The instruction sets of MCU products from different manufacturers are different, especially the different instruction set system architectures. For example, the widely used MCS51 series and PIC series microcontrollers adopt CISC instruction system and RISC instruction system, respectively. Microcontrollers can be classified into several types according to their instruction set, such as CISC, RISC, and RISC-like. The traditional MCS51 controller is a CISC type, which has a high code density, but most instructions require multiple clock cycles to complete. RISC type generally has a lower instruction density, but the instruction efficiency is very high. RISC-like type combines the advantages of CISC and RISC. The reason why RISC and RISC-like have such high instruction efficiency is due to the hardwired structure and pipelined structure brought about by the small instruction set. The simple instruction set can be decoded by hardwired, without the need for microcode control, which improves the decoding efficiency. The pipelined structure divides the instruction into several steps to complete. When the pipeline is full of work, the average execution time (CPI) of each instruction is about one clock cycle [3]. Generally speaking, RISC is 50%-70% faster than the equivalent CISC, and is also easier to design and correct. Therefore, the current product development and research design of 8-bit microcontrollers are mainly based on compatibility with products that have been widely adopted by customers in the market, continuously improving performance and reducing power consumption to adapt to market competition and technological development. For microcontrollers originally based on the CISC instruction set, the RISC concept has been gradually incorporated into the numerous updates. For microcontrollers using the RISC instruction set, the focus remains on continuously optimizing and improving the entire architecture to meet the demands of high performance and low power consumption, especially in terms of pipeline structure improvements. This article is proposed under this context, primarily discussing the design techniques of 8-bit microcontrollers based on the RISC architecture. 3. Structural Features and Design Principles of RISC Microprocessors Although there are still different opinions in the industry about what characteristics a RISC processor should have, various RISC architectures have some commonalities[4]: (1) They adopt a Harvard bus structure, and most instructions are completed in one clock cycle to facilitate pipelining; (2) They adopt an independent and simple load/store structure; (3) Instruction decoding is usually implemented by hard-wired rather than micro-decoding to speed up execution; (4) Most instructions have a fixed format to simplify instruction encoding and decoding; (5) They have a small instruction set and a few addressing modes; (6) The data channel is piped to make the processing highly parallel; (7) They adopt a large-capacity high-speed register file (or register file) to avoid exchanging data with the slower system RAM as much as possible. They try to store the operation data in registers to reduce the number of times memory is accessed. Based on the above discussion, the following focuses on the key technologies of 8-bit RISC microcontrollers in design from the perspective of system architecture, in terms of high performance and low power consumption. 4. Key Technologies 4.1 Selection of RISC Instruction Set The use of a controller system is closely related to the specification interface between software programming and hardware design; this interface is the microcontroller's instruction set. The Instruction Set Architecture (ISA) is a prerequisite for microprocessor hardware-software co-design. The instruction set must be complete, ensuring that all computable functions are implemented within a reasonable program space; moreover, the instruction set must be efficient, allowing commonly used functions to be implemented with relatively few instructions. Therefore, a microcontroller system provided for application software development must have a complete and efficient instruction set. The instruction set directly determines the microcontroller's internal hardware structure and is also the basis for compiling user programs into target code. The final determination of the instruction set is closely related to and mutually restrictive of the program memory, data memory, register variables, and memory addressing modes required by the entire system. Each component, and even a specific byte, should have a unique address so that the instruction set can correctly identify and operate on each component or byte. Therefore, there are a series of different measures for different products: 1) weigh the length of the instruction from the required address and the corresponding increase of registers; 2) classify the instructions and determine the instruction byte format of each type to simplify the decoding logic of the operation control signal; 3) increase the corresponding registers to make up for the lack of instruction byte length; 4) the allocation of instruction byte format should take into account the structural complexity of the corresponding components and the corresponding addressing mode; 5) whether memory, registers and I/O ports are uniformly addressed. The above list is not detailed and there is no order of priority. They should be analyzed at the same time. The performance, power consumption and design complexity of the corresponding measures are different and should be considered in a unified manner. The power consumption analysis of ISA should be considered from the aspects of instruction code capacity and instruction execution efficiency. The selection of technologies such as instruction set size, register variables, memory addressing mode and pipeline structure are closely related to instruction code density. Research has found that appropriately adding some specific complex instructions to the RISC reduced instruction set is a feasible way to improve code density and ensure high performance and low power consumption of the processor. Therefore, the instruction set that can generate high instruction code density is undoubtedly the first choice for RISC low power design [5]. 4.2 Paging Design of Register Files with Shared Area The most important feature of the RISC design concept is that all operations are register-oriented. Data transfer is performed using register-to-register operation instructions, which speeds up the process and simplifies the instruction control logic, reducing the chip area of ​​the control unit composed of hardwired logic. Fixing the number of bits of the register address in the instruction inevitably limits the number of registers, but the segmentation and paging design concept of high-end processors can expand the addressing range. The fundamental starting point of the segmentation and paging design concept is to decompose the linear address of the memory into two-dimensional or multi-dimensional addresses; only the lowest dimension address is expressed in the instruction, while other facilities (such as segment number registers and page number registers) are used to store the higher dimension address. Generally, the register file is divided into several pages, each page has a fixed size, and only the page address of the register is used in the instruction. A page number register is set in the system special register, and the access to different page registers is switched by changing its contents [6]. To overcome the various shortcomings of simple paging mechanisms, a paging design with a shared area is usually adopted. This not only reduces the number of bits in the register logical address in the instruction, but also allows access to system registers at any time, and facilitates the exchange of information between different page registers through general-purpose registers in the shared area. Of course, there must also be corresponding methods and measures for mapping logical addresses to physical addresses. 4.3 Paging Design of Program Space Due to the same reasons as register files, using the complete program space address in the instruction will limit the size of the program space. Therefore, the program space usually adopts the design concept of paging, and a common program area is set in different pages (if the instruction length fully meets the requirements of the program space address, this concept is not needed). Its design concept is similar to the register paging design with a shared area, and will not be elaborated here. The only difference from the register common area is that the program common area provides a platform for the program to jump between different pages. 4.4 Pipeline Technology Pipeline design is inseparable from the 8-bit RISC microcontroller architecture and is the core of the entire system design. Its selection directly affects the system's performance and power consumption. Pipeline technology can make the most of microcontroller resources, so that each component works in every clock cycle, which greatly improves efficiency. However, due to the strong dependency between the various stages of the pipeline, if not handled properly, the execution of instructions will not achieve the expected results. Therefore, it is necessary to be familiar with the pipeline's dependencies and transfer issues. One is resource conflict, that is, competing for the same functional component at the same time, which is generally simultaneous access to memory, which requires a pause in the pipeline. The second is data dependency conflict, which has three types: RAW, WAR, and WAW. To resolve this conflict, an internal pass-through structure or a delay in the pipeline is used. The third is control transfer conflict, that is, for conditional jump instructions, it is necessary to determine whether to jump based on the calculation result before determining the new PC value. The calculation result is obtained after the execution stage, which causes the pipeline to lose a lot of performance. Generally, the conflict is resolved by adding hardware to obtain the calculation result in advance [3]. The longer the pipeline, the more severe the dependency and transfer problems become. On the one hand, it greatly increases the complexity of the hardware control circuit; on the other hand, the pauses in the pipeline cycle lead to an increase in CPI and a decrease in system performance. Therefore, a longer pipeline is not necessarily better; finding a balance between speed and efficiency is paramount. In the pipeline design of 8-bit RISC microcontrollers, there are many schemes. Different schemes correspond to different areas, speeds, and power consumption. The specific selection should be considered from multiple perspectives. First, various specific pipeline structure schemes and their required strict timing should be derived from the system's operating speed requirements and the number and depth of pipeline stages. Then, the advantages and disadvantages of each scheme should be judged based on factors such as system power consumption, area, performance, and the design complexity caused by pipeline dependency and transfer problems. Finally, the optimal scheme that meets the requirements should be selected through compromise. 4.5 Low power technology With the rapid development of the semiconductor industry, integrated circuits have entered the deep submicron stage. The clock frequency and chip integration of microprocessors have been continuously improved. Power consumption has become the primary concern in many design fields. This is most prominent in high-performance microprocessors and portable electronic devices [7]. When designing hardware and software co-designs and determining the instruction architecture according to the system function description, the power consumption results caused by different design starting points will vary greatly. Therefore, the determination of the entire system architecture is undoubtedly the primary issue to be considered in low power consumption. It mainly reflects the following aspects [5]: 1) Optimize the instruction set as much as possible according to the functional requirements and simplify the decoding and execution units of the system; 2) Achieve a low power structure by developing hardware parallelism and pipelined execution of functional units; 3) Set the capacity of memory and registers reasonably to reduce the number of buses required; 4) The division of each sub-module of the system hardware and the setting of different working states in the software are very important for power consumption optimization. 5. Conclusion In today's increasingly widespread application of microcontrollers, higher requirements are put forward for microcontrollers. It is hoped that they will be faster, consume less power, be cheaper, be easier to learn and use, and have fewer peripheral devices when forming a system. Therefore, research on the product development and design of 8-bit microcontrollers, which are currently the most widely used, is particularly important. Furthermore, the architecture design is the most crucial aspect of the entire design process; all subsequent work depends on the designed architecture. This paper analyzes and discusses the key technologies employed in 8-bit RISC architecture and the issues that should be considered, which has certain research value and significance. References: [1] Zhang Zhi. Analysis and design of VLSI of 8-bit RISC microcontroller [D]. University of Electronic Science and Technology of China. 2003.5; [2] Chen Ruisen, Guo Donghui. Embedded MCU design based on CISC/RISC hybrid architecture [J]. Computer Application Research 2006, (8): 194-196 [3] Li Xia, Shen Bo, Ji Longwei, Zhang Qianling. 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