0 Introduction In today's rapidly developing world of the Internet and local area networks, while computers are interconnected, data acquisition and control in various home appliances, instruments, and industrial production are becoming increasingly networked. Ethernet, due to its ubiquity and low interface cost, has become the most common network widely used in production and daily life. On the other hand, embedded devices, in terms of price, size, and real-time performance, are unmatched by general-purpose computers and are also widely used in automation control, data acquisition, and communication networks. Therefore, embedded Ethernet technology has broad prospects, and the first problem to be solved is the embedded Ethernet interface issue. This paper designs an embedded Ethernet interface based on the most commonly used embedded processor S3C44B0X and Ethernet driver RTL8019AS. The design is characterized by its simplicity and ease of use, allowing for expansion with other modules and, if necessary, porting of an operating system for application in other complex fields. This paper starts with the internal structure and working principle of the RTL8019AS, introduces the hardware interface circuit based on S3C44B0X, and details the design of the hardware-layer driver in C language. 1. Ethernet Frame Structure A standard Ethernet physical transmission frame consists of seven parts: PR (synchronization bit), SD (separator bit), DA (destination address), SA (source address bit), TYPE (type field), DATA (data segment), and FCS (frame check). Its transmission frame structure (and the length of each part) is shown in Figure 1. Except for the variable length of the data segment, the lengths of the other parts are fixed. The data segment is 46 to 1500 bytes. Ethernet specifies that the maximum length of the entire transmission packet cannot exceed 1514 bytes (14 bytes for DA, SA, and TYPE), and the minimum cannot be less than 60 bytes. When padding is required, the number of padding characters is not included in the length field; if the length exceeds 1500 bytes, it must be split into multiple frames for transmission. In fact, when sending data, the PR, SD, FCS, and padding fields are automatically generated by the Ethernet controller; when receiving data, PR and SD are skipped, and the controller considers the reception of data to have started once it detects a valid preamble field (i.e., PR and SD). 2. Chip Introduction The S3C44B0X is a 16/32-bit RISC (Reduced Instruction Set Computer) processor manufactured by Samsung using the ARM7TDMI core. It offers a rich set of built-in modules, including: 8 kB cache and internal SRAM, LCD (Liquid Crystal Display) controller, 2-channel UART, 4-channel DMA (Direct Memory Access), memory management, timers with PWM (Pulse Width Modulation), I/O ports, an 8-channel 10-bit A/D converter, IIC and IIS buses, synchronous SIO interface, and PLL (Phase Locked Loop) frequency multiplier. Interface expansion is possible as needed, and its low cost has led to its widespread use in embedded systems. The RTL8019AS is a widely used and cost-effective network control chip in embedded systems. The main features of the RTL8019AS include: compliance with Ethernet II and IEEE 802.3 (10Base5, 10Base2, 10BaseT) standards; full-duplex operation with simultaneous transmit and receive speeds up to 10 Mbit/s; built-in 16 kB SRAM for transmit/receive buffering, reducing the speed requirements on the main processor; support for 8/16-bit data buses, 8 interrupt request lines, and 16 I/O base address selections; support for automatic UTP, AUI, and BNC detection, and automatic polarity correction for 10BaseT topology; and programmable output from 4 diagnostic LED pins. The RTL8019AS can be divided into the following functional modules: a) Remote DMA interface: the connection channel between the processor and the RTL8019AS transmit/receive buffers, allowing the processor to perform remote DMA operations only. b) Local DMA interface: the connection channel between the RTL8019AS and the network cable, facilitating data exchange between the controller and the network cable. c) MAC (Media Access Control) logic: automatically controlling remote and local DMA data packet transmission and interrupt generation. d) Address identification logic: Compares the destination address in the received data frame with the address in the address register to determine if it is a frame destined for the local machine. e) CRC (Cyclic Redundancy Check) generation and verification logic: Generates a CRC code when sending data and performs a CRC check on the received frame. f) Protocol PCA: Responsible for implementing the Ethernet specification. The RTL8019AS has 16kB of SRAM, divided into 64 pages, 256 bytes/page, forming a circular queue as the transmit and receive buffer. Operations can only be performed on a page basis, with page addresses ranging from 0x4000 to 0x7FFF. The buffer can be set and its status read through related register read and write operations. Since the receive buffer operates on a page basis (256 bytes), the registers related to the buffer address only need to store the high 16 bits of the buffer address. In this design, the first 32 pages (0x400 to 0x5FFF) are used as the receive buffer, and the last 32 pages (0x6000 to 0x7FFF) are used as the transmit buffer. The RTL8019AS has a 32-bit I/O address space with address offsets from 00H to 1FH. Of these, 16 addresses (00H to 0FH) are register addresses. Remote DMA addresses (10H to 17H) can all be used as remote DMA ports; only one needs to be used. The reset port (18H to 1FH) consists of 8 addresses with the same function: resetting the RTL8019AS. The RTL8019AS's internal I/O base address is 00H, but the address the microprocessor needs to access is not 00H; this address is determined by the connection between the processor and the network controller. The RTL8019AS registers are divided into four pages (PAGE0 to PAGE3), each with an address offset from 0x00 to 0x1f. The page to be accessed is determined by the PS1 and PS0 bits in the RTL8019AS's command register (CR). Registers within each page are addressed by SA0 to SA3. The registers on pages 0 and 1 are crucial, used for data transmission and reception control and interrupt management, and must be configured before use. Pages 2 and 3 are used only for diagnostics and other configurations, and are rarely used. 3. Design Concept First, the S3C44B0X configures its relevant registers through the I/O ports of the RTL8019AS. During communication, data exchange between the S3C44B0X and the RTL8019AS's transceiver buffers is controlled by remote DMA, while data exchange between the RTL8019AS's transceiver buffers and the Ethernet bus is controlled by its local DMA. The RTL8019AS notifies the S3C44B0X of the data transmission and reception results and status via interrupts. The S3C44B0X then queries the interrupt status register and takes appropriate action. The system structure is shown in Figure 2. 4. Interface Circuit Design The interface circuit is shown in Figure 3. The nOE and nWE pins of the S3C 44B0X are connected to the IORB and IOWB pins of the RTL8019AS, respectively, to control data read and write operations; they are active low. The RTL8019 uses interrupt 0, corresponding to external interrupt 1 of the S3C4480. The RTL8019AS has three operating modes: a) Jumper mode: I/O and interrupts are determined by jumpers; b) Plug and Play (PNP) mode: Automatic configuration is performed by software; when using this method, the system boot program must include functions that support PNP; c) Jumperless mode: I/O and interrupts are determined by the contents of the external EEPROM 93C46. In this design, to reduce the complexity of the boot program and interface circuit, the jumper mode is selected, so JP is connected to a high level. X1 and X2 are the input and output terminals of the 20 MHz crystal oscillator, respectively. LEDs 0-2 are connected to three light-emitting diodes to indicate network connection, data transmission, and transmission status. The 20F001 is a network card filter, internally containing a pair of low-pass filters and a pair of isolation transformers. Its outputs TX+/- and RX+/- are connected to the RJ45 signal ports. Since the AEN pin of the RTL8019AS is connected to the nGCS2 pin of the S3C44B0X in this design, the starting address of the S3C44B0X memory is 0x0600-0000. Furthermore, since IOS0-IOS3 of the RTL8019AS are grounded, in jumper mode, when IOS0-IOS1 are 0000, the base address of the RTL8019AS is 0300H. Therefore, in this design, the S3C44B0X accesses the base address of the RTL8019AS from 0x0600-0300. 5. Driver Design 5.1 Program Design Ideas In this design, the driver mainly contains three functions: the system initialization function, the data packet receiving function, and the data packet sending function. The initialization part completes the initialization work of RTL8019AS before use, including setting the registers of the relevant working mode, allocating and initializing the receive and transmit buffers, and initializing the network card receive address. MAR0-MAR7-Multipoint address registers: The values ​​of these 8 registers are generated according to the values ​​of the multicast address array, providing filtering of multicast addresses and filtering out some multicast data packets that do not belong to it. Here they are all set to FFH to receive data packets of all multicast addresses: The following 6 statements set the MAC address, and the registers are PAR0～PAR5: actual address registers. These registers are used to compare the data packets of the target address to determine whether to receive or reject them. The address is placed in the array add[6]. 5.2 Data transmission and transmission Data transmission and transmission are completed by local DMA transmission and remote DMA transmission. Most of the work of the former is automatically completed by RTL8019AS. What we need to do is set the size of the receive and transmit buffers and pointer variables. These tasks have been completed during the initialization of RTL8019AS, so we only need to write remote DMA read and write functions. For reading and writing to the remote DMA port, the only difference is the direction of data transmission. Here, we only take the read operation as an example, that is, writing the function to retrieve data packets from the RTL8019AS receive buffer to the S3C4480X. (Note: The write function of the remote DMA, that is, the function to write data to the RTL8019AS send buffer—send_data(), is omitted.) 5.3 Ethernet Interface Communication Function Flow Here, a combination of interrupts and polling is used to determine whether to send and receive data. When any interrupt bit in the ISR (Interrupt Status Register) of the RTL8019AS is set, the S3C4B0X must respond to the interrupt (here we only focus on the 0th and 1st interrupt bits, that is, reflecting that the RTL8019AS has correctly received data and successfully sent data packets, respectively; therefore, other bits are masked in the initialization function). At this time, the ISR needs to be accessed to determine what kind of interrupt it is, and then make the corresponding response, as shown in Figure 4. 6 Conclusion This design has been debugged in terms of both hardware and software and has successfully carried out Ethernet data transmission. Due to the S3C4480X's outstanding cost-effectiveness and rich peripheral interfaces, this design can be extended to many fields such as embedded instruments, industrial data acquisition networks, and embedded network control.