Introduction In the design of a software-defined radio (SDR)-based wireless communication signal acquisition platform, the signal received by the antenna is processed by a frequency converter and an A/D converter, and then sent to the main control board for data distribution processing via a high-speed channel. The system block diagram is shown in Figure 1. [align=center] Figure 1 System block diagram of the main control board[/align] The hardware core of the main control board is the embedded microprocessor MPC8260, which is responsible for loading system software, distributing data, and interacting with external command control. On the software side, the high-performance VxWorks embedded real-time operating system is used. The RF signal received from the antenna, after frequency conversion and A/D conversion, is connected to the FPGA as a data source. The FPGA performs preprocessing such as intermediate frequency conversion and channel estimation on the received data, and then transmits the data to local memory under the control of the CPU. Finally, the CPU packages the data and distributes it quickly. Therefore, transmitting a high-speed data stream of 40–50 Mbps from the FPGA to the CPU is a key aspect of the system design. If the CPU is required to transmit each byte of data, the data transmission rate will be very low, regardless of whether interrupt-driven or program polling is used, which cannot meet the system requirements. Compared to general program-controlled data transfer methods, DMA (Direct Memory Access) has advantages such as high data transfer speed, short I/O response time, and low CPU overhead. Therefore, DMA is chosen as the transfer mode, allowing data in the FPGA to be stored directly in local memory without passing through the CPU's internal registers. The MPC8260 supports multiple DMA implementations, suitable for different data transfer source/destination devices, different data block sizes, and storage modes. Therefore, a suitable DMA transfer interface needs to be designed according to the system characteristics of the main control board. 1 DMA System Structure of MPC8260 [align=center] Figure 2 CPM Principle Block Diagram[/align] The MPC8260 is an embedded PowerPC microprocessor designed by Freescale mainly for the data communication field. It has a dual-core structure: a high-performance MPC603e 64-bit RISC microprocessor core and a 32-bit RISC Communication Processor Module (CPM) specifically designed for communication. The CPM can offload most of the peripheral communication tasks from the PowerPC core, including two DMA controllers, namely Serial Direct Memory Access (SDMA) channels. Therefore, this dual-processor architecture has stronger communication control capabilities than a single-processor architecture. The block diagram of the CPM is shown in Figure 2. In addition to the PowerPC core and CPM, the MPC8260 also includes a flexible System Interface Unit (SIU) primarily used for controlling the interface with external buses. In Figure 2, besides the SDMA module, the CPM also includes a Communications Processor (CP), dual-port RAM, and control interfaces for some serial peripheral devices. The SDMA is connected to the 60x bus and the local bus, and can directly access the dual-port RAM inside the CPM. The CP uses these two SDMAs to provide two virtual SDMA channels for each peripheral serial controller: one for input and one for output. Simultaneously, the CPM uses these two physical SDMA channels to simulate four programmable, independent DMA (Independent DMA, IDMA) channels for data transfer between memory and memory, and between peripherals and memory. The FPGA and SDRAM on the main control board are both connected to the 60x bus of the MPC8260, so IDMA can only be used to achieve DMA transfer between them. Depending on the triggering method for transmission initiation, IDMA can be divided into two types: IDMA transfer controlled by handshake signals and IDMA transfer controlled by CP commands. The characteristics of each method are described below. 1.1 IDMA Transfer Controlled by Handshake Signals IDMA transfer controlled by handshake signals is mainly used for data transfer between peripherals and memory. Each IDMA channel has three handshake signals for transmission handshake control: DMA request signal DREQ [1~4], DMA acknowledge signal DACK [1~4], and DMA end signal DONE [1~4]. In this method, the PowerPC kernel only needs to participate in the IDMA channel initialization; the subsequent transmission process is entirely controlled by the CP according to the channel parameter settings and handshake signals, maximizing kernel freedom. The disadvantages of handshake signal control are: ① Synchronization between data in SDRAM and data in the MPC8260 is relatively complex. ② Bus arbitration is required after each request signal is sent, and only the peripheral port size or 32 bits of data can be transmitted at a time after obtaining bus access, resulting in low bus utilization. ③ The handshake control logic and timing are relatively complex, increasing the burden on the FPGA's internal control logic design. Although this transmission method basically does not occupy core resources, due to the limited bus bandwidth and low utilization, the core may be unable to obtain bus access for a long time and remain in a waiting state under continuous high-speed communication conditions. Therefore, IDMA controlled by handshake signals is generally only suitable for peripheral-initiated data transmissions that are not too frequent. 1.2 IDMA Transmission Controlled by CP Command The IDMA of the MPC8260 can also be internally triggered by writing the START_IDMA command to the CP command register. After each transmission is started, the PowerPC core is released, and the parameters such as the source address, destination address, and data length are controlled by the CP according to the information initialized in the IDMA channel. The maximum length of each transmission is 4 GB. Compared to IDMA transfer controlled by handshake signals, this method requires the PowerPC kernel to initiate each transfer via command in addition to initializing the IDMA channel, thus consuming more kernel resources. However, a maximum of 4 GB of data can be transferred after a single transfer is initiated, so the additional overhead of writing a register is negligible as long as the data length of each transfer is relatively long. Furthermore, since the internal command triggering method does not require handshake signals and avoids frequent competition for bus control every few bytes, this method offers higher transfer efficiency and faster speed. The internal command triggering method trades space for time—using a large front-end buffer to improve transfer speed. Considering that the bottleneck of the main control board's hardware and software systems lies in bus bandwidth, while storage resources are relatively abundant, IDMA transfer controlled by CP commands is chosen as the data transfer method from the FPGA to SDRAM. The data transfer interface design between the FPGA and MPC8260 is shown in Figure 3. The FPGA on the left is connected to the MPC8260 on the right via 16 data lines, 10 address lines, 2 interrupt request lines, and some read/write control signal lines. The MPC8260 is connected to local SDRAM via a 64-bit data bus. [align=center] Figure 3 IDMA Transfer Design Block Diagram[/align] The FPGA internally allocates two large storage spaces for alternately buffering data received from the data source. When either buffer is full, the continuously received data is saved to the next buffer, and an interrupt triggers the MPC8260 to start the corresponding IDMA channel to transfer the data to SDRAM. IDMA control, data synchronization, and error handling are all handled by the MPC8260; the FPGA is only responsible for sending and receiving data and triggering interrupts. The program design for each is described below. 2.1 MPC8260 Program Design The internal program processing flow of the MPC8260 is shown in Figure 4. The MPC8260 pre-initializes the two IDMA channels: the source address and data length of the channel correspond one-to-one with the buffers in the FPGA. Upon receiving an interrupt signal from the FPGA, if the corresponding IDMA channel is idle, a CP command is issued in the interrupt handler to start receiving data, and the corresponding IDMA channel is set to busy state. Otherwise, unread data may have been overwritten in the FPGA, and the MPC8260 enters the error handling routine. At the end of data transmission, the DMA controller sends an internal CPM interrupt to the kernel. In the interrupt handler, the IDMA channel parameter settings are restored, and the IDMA channel is set to idle state to await the start of the next transmission. The core of the MPC8260 program is the IDMA channel setup and interrupt handling. [align=center] Figure 4 MPC8260 Transmission Processing Flow[/align] 2.1.1 IDMA Channel Setup Similar to general DMA channel setup, the main parameters of IDMA channel setup include: source address, destination address, and data length. In addition, the MPC8260 IDMA channel setup also includes channel mode, buffer, and interrupt configuration, involving many registers and making the configuration complex. The logical structure of the IDMA channel setup is shown in Figure 5. [align=center] Figure 5 Logical structure block diagram of IDMA channel settings[/align] The BD (Buffer Descriptors) table is a data structure used to specify basic information such as transmission mode, source/destination address and data length. The base address of the BD table is specified by the value of the IBASE register in the parameter RAM. In addition to the base address of the IDMA BD table, the IDMA parameter RAM also stores IDMA channel information such as the IDMA BD pointer, the starting address of the IDMA transmission buffer, the size of the IDMA transmission buffer and the DMA channel mode. The base address of the IDMA parameter RAM is specified by the value of the IDMAx_BASE register in the parameter RAM. The address of the IDMAx_BASE register is fixed, such as IDMA1_BASE at the offset RAM base address 0x87FE. CP finds the IDMA parameter RAM through the IDMAx_BASE register and then finds the BD table through IBASE to initialize the IDMA channel in sequence. For specific register configuration, please refer to the IDMA programming example in Chapter 19 of reference [1]. To improve the channel transmission rate, the following points should be noted during IDMA channel initialization in the system: ① UPM mode needs to be configured in the SIU to control burst read/write between the MPC8260 and the FPGA. Do not use the General Purpose Chip Select Machine (GPCM) mode. Because the GPCM mode controlled by the MPC8260 memory does not support burst transfers, IDMA operating in GPCM mode will only perform normal single read/write operations regardless of whether the length of the transmitted data meets the burst requirement. ② Treat the FPGA as memory, and operate IDMA in memory-to-memory dual-address mode, with the buffer set to a maximum of 2 KB. ③ The BD table configuration should correspond one-to-one with the buffers in the FPGA. The CM (Continuous Mode) bit in the BD table structure should be set to buffer chain mode. After each BD table transfer is completed, the valid bits of the BD table should be cleared; simultaneously, the CP automatically loads the IDMA register according to the value of the next BD table for subsequent transfers. After IDMA channel initialization, wait for the CP to issue the START_IDMA command to begin transmission. An interrupt signal is triggered at the end of the last BD table transfer to notify the PowerPC kernel of the completion of this transmission process. The channel setting registers that change during transmission include the IDMA BD table pointer, source address, destination address, and BD table valid bits. Therefore, these registers need to be restored in the interrupt handler after the BD table transmission ends to prepare for the next transmission. 2.1.2 The interrupt handling system design uses two types of interrupts: external interrupts introduced by the IRQ pin and internal interrupts triggered by CPM. The initialization process includes: enabling the corresponding interrupt mask bit, selecting the interrupt priority, connecting the corresponding interrupt vector number and interrupt service routine, etc. To ensure good real-time transmission, the interrupt priority needs to be set as high as possible. The difference from the general interrupt handling process is that the MPC8260 interrupt handling controller uses a hierarchical structure to expand the total number of interrupt signals. The interrupts in CPM are level two interrupts, which need to be controlled by two levels of interrupt controllers: the CPM interrupt controller and the SIU interrupt controller. In this design, the interrupt used to notify the kernel that the current transmission process has ended is the signal BC (BD Completed) indicating the end of the last BD table transmission in CPM. The BC signal, along with several other signals such as command completion, sends an interrupt signal to the kernel through the IDMA bit in the SIU interrupt pending register. Therefore, during interrupt initialization, the corresponding bits of both the IDMA mask register and the SIU interrupt mask register must be enabled simultaneously. A specific example of interrupt initialization is as follows: It is particularly important to note that clearing the SIU interrupt pending register before the interrupt handler ends cannot be done by directly writing 1 to the IDMA bit of the SIU interrupt pending register. Instead, it must be done indirectly by writing 1 to the BC bit of the IDMA event register. 2.2 FPGA Part The FPGA chip used in the program system is the Xilinx Virtex II 3000. The large-capacity BlockRAM embedded in the Virtex II is configured as a single-port RAM for buffering. This can be generated using the built-in IP core of Xilinx's ISE 7.1i integrated development environment. For the FPGA, since data input/output is sequential, only one address line is needed at each end to distinguish between adjacent data. The address line, together with the internal counter, forms a read/write pointer. When the write pointer jumps from one half of the buffer to the other half, a corresponding interrupt signal is emitted. The key part of the FPGA design is the bus interface design with the MPC8260. By appropriately selecting the starting address and length of the buffer, the MPC8260 can perform burst reads from the FPGA. In the design, the MPC8260's burst reads and writes to the FPGA follow its configured UPM mode, so the UPM mode design and FPGA read/write logic design must be considered comprehensively. When designing the UPM mode, a falling edge can be generated by the General Purpose Line (GPL) before each time the MPC8260 locks the data bus to notify the FPGA to write new data to the data bus; or the GPL can be used to send the bus clock to the FPGA to achieve transmit/receive synchronization and complete the read/write between the MPC8260 and the FPGA. 3. Summary Combining the interrupt handling of the MPC8260 and the IDMA transfer mechanism, a high-speed data transfer interface between the MPC8260 and the FPGA was designed. Test results show that copying data from the FPGA to SDRAM using a loop read method results in a data transfer rate of only about 11 Mbps; while using the IDMA method described in this paper, the maximum rate can reach 500 Mbps, with a lower core utilization rate. The experimental results fully meet the system design requirements. This study provides some reference value for the interface design of PowerPC series CPUs. References [1] Freescale. MPC8260 PowerQUICCTM II Family Reference Manual. MPC8260RM Rev.2, 2005-12. [2] Freescale. MPC8260 PowerQUICCTM II IDMA Functionality. Rev. 3, 2006-02. [3] Freescale. MPC8260 IDMA Timing Diagrams. Rev. 4, 2006-07.