Introduction At present, wireless sensor network hardware platforms can be classified in various ways, such as node controller type, node wireless communication type, and node operation characteristics. Since wireless sensor networks mainly focus on the state information of a certain range within the detection area rather than a specific point, the method of classifying according to node operation characteristics is more scientific, as it covers the specific implementation forms of nodes. According to this method, wireless sensor networks can be divided into four categories[1]: specific sensor platforms, general sensor platforms, high-bandwidth sensor platforms, and gateway platforms. Specific sensor platforms focus on the ultra-low power consumption and miniaturized size design of nodes, but this also determines that their processing and transmission capabilities are very limited. For example, UCBerkeley's Spec[l] is a node that integrates a processor, RAM, communication interface, and sensor on a 2.5mm×2.5mm silicon wafer. It can operate continuously for several years powered by an attached miniature battery, but its prototype version only has a unidirectional communication link. Another example is SmartDust, developed by UCBerkeley with the support of the DAR-PA/MTOMEMS program. It is also an ultra-miniature node with a design target volume of about 1mm3. Due to the use of optical communication and the adoption of both active and passive working modes, its power consumption can be further reduced. General-purpose sensor platforms have relaxed the requirements for size and focus on the scalability and testing needs of nodes, but they still have strict requirements for node power consumption. This type of platform is currently the most widely used in experimental research and productization. UCBerkeley's Mica series nodes are the main representatives of this type, including different versions such as Rene, Mica, Mica2, Mica2dot, and Mica-Z. General-purpose sensor platforms have relaxed size requirements, focusing on node scalability and testing needs, but still have strict requirements on node power consumption. This type of platform is currently the most widely used in experimental research and productization. UCBerkeley's Mica series nodes are the main representative of this type, including different versions such as Rene, Mica, Mica2, Mica2dot, and Mica-Z. Gateway platforms are an indispensable part of wireless sensor networks, typically having higher processing power and interface bandwidth than other types. They enable data exchange between wireless sensor networks and other types of networks, or between different wireless sensor networks, through a general-purpose interface using protocol conversion functions. 1. Network Architecture and Node Design 1.1 Network Architecture Design The system network architecture is shown in Figure 1. Multiple terminal nodes and a sink node determine the detection area. Monitoring data from each node is transmitted to the gateway node (gate) through a self-organizing multi-hop routing network; then, it is transmitted to the gateway computer via a serial communication interface and connected to the Internet. Remote monitoring terminals can obtain monitoring data within the monitoring range via the Internet. In this network, both gateway access devices and monitoring terminals can be implemented using traditional computers. The following focuses primarily on terminal nodes, aggregation nodes, and gateway nodes. In terms of data processing intensity, due to the tree-like network structure, terminal nodes handle the least amount of data, only needing to acquire and send data during specific detection events. Aggregation nodes handle slightly more data, receiving data from multiple terminal nodes and performing preliminary processing before sending it to the next aggregation or gateway node. Gateway nodes handle the largest amount of data, receiving data from the entire detection area and processing it through parsing, fusion, and protocol conversion before sending it to the Internet. Regarding energy demand, terminal nodes consume the least energy, followed by aggregation nodes. However, both types of nodes typically rely on their own limited energy resources and cease operation once depleted. While gateway nodes consume a large amount of energy, they can be continuously supplied with external power, allowing for less stringent power consumption requirements. Therefore, the energy consumption of terminal nodes and aggregation nodes is strictly controlled and optimized at multiple levels to maximize the effective operating time of the entire network. 1.2 Node Design Since wireless sensor networks are a typical self-organizing network, their topology will change as nodes join, leave or move, and the functions of each node in the network will also change dynamically. Therefore, nodes in the monitoring area should have the ability to act as terminal nodes or aggregation nodes. Terminal nodes and aggregation nodes can be collectively referred to as "ordinary nodes", and their hardware structure is shown in Figure 2. An 8-bit RISC structure low-power MCU was designed and implemented in the ordinary node as the system control core, which will be described in detail later; the memory SST29VE020 is used as external program memory with a capacity of 256KB; the A/D converter MAX152 is used to convert the voltage signal after conditioning of the external sensor into a digital signal; the radio frequency transceiver module uses the CC2420 of Chipcon that supports the ZigBee protocol [2]. The gateway node is similar to the ordinary node in structure, but the working environment is different and the functional requirements are increased. It can be implemented by expanding the ordinary node. The design of 28-bit RISC low-power MCUs in existing wireless sensor network node hardware designs mostly uses general-purpose processor units widely used in embedded fields, without developing dedicated control cores for wireless sensor network applications. Therefore, node designs are limited by size, power consumption, interfaces, and resources, and in some designs, resources are even wasted. This is very detrimental to the low-power and miniaturized design of nodes. Therefore, this design proposes and implements an 8-bit RISC low-power MCU as the node control core. 2.1 MCU Structure Design The MCU hardware structure is shown in Figure 3. In this design, the MCU adopts an instruction set compatible with ELAN's EM78 series MCUs for prototype development. The CPU uses a two-stage pipeline, employing a two-phase clock control to complete the instruction prefetch operation. After the jump instruction, a no-operation (NOP) instruction is automatically added to control the transfer operations. Currently, with the same bus clock frequency, the operating speed of this CPU is twice that of the EM78 series MCUs. The MCU's external program memory uses a 256K×8-bit structure, but in actual use, it is constructed from adjacent odd and even address units to form a 128K×16-bit structure to meet the requirements of a 13-bit instruction set. Register R2 (PC), used for instruction fetching, is 17 bits wide, with the high 7 bits used for addressing the 128 pages of program memory and the low 10 bits used for intra-page addressing. Register R5 stores the current working page address, which is determined and passed to R2 by the instruction decoder. This addressing method is beneficial for operating Flash memory, which also uses a paging structure in its physical architecture. The MCU's on-chip memory includes 4KB of data RAM, 128 bytes of general-purpose register RAM, and other special registers. To reduce the CPU's direct addressing range and meet the requirements of a fixed short-word instruction set, the memory uses a unified organization method of paging, block partitioning, and mapping. Special registers include the MCU's module registers and I/O registers, divided into 6 pages, each with a maximum of 16 bytes. Page switching is performed using register R3. Since registers do not completely occupy the address space, the missing portions are reserved for future expansion. The 128-byte general-purpose register RAM is divided into four blocks of 32 bytes each, with block switching performed using register R4. Although divided into blocks, both direct and indirect addressing modes are still designed, improving operational flexibility. This space is primarily used by variables in the program, and the block structure saves address space while enhancing the protection mechanism between function variables, which is beneficial for embedded operating system applications. The 4KB data RAM is mapped into paged data registers, accessed through a 16-bit address interface and an 8-bit data interface, significantly reducing the direct addressing space. While this memory organization method currently increases some data access overhead, it does not affect the performance of node systems with low computational loads, and the code can be optimized for this structure at the compiler level. The advantages of this approach are simplified CPU hardware structure, significantly reduced node size, and lower power consumption, which is generally beneficial for node system construction. The MCU has eight external interrupt sources and five internal interrupt sources. The eight external interrupt sources share pins with port PORT7 and can be configured with rising or falling edge trigger modes to meet the needs of different peripheral interfaces. Five internal interrupt sources originate from the TCC, COUNTER1, COUNTER2, UART, and SPI modules. The TCC module utilizes an external clock for timing operations, providing basic hardware support for the operating system to divide time slices. COUNTER1 and COUNTER2 use internal bus clocks for counting; in addition to basic counting and timing functions, they can also be used in conjunction with external interrupt pins to implement input capture or output comparison functions. The interrupts from the UART and SPI modules are primarily used for communication service programs. 2.2 Low-Power Considerations in the Design Due to the application characteristics of wireless sensor networks, their design must revolve around low power consumption. Therefore, the low-power design of the MCU, as the core of node control, is also quite important. Low power consumption is considered from three aspects at the system and logic levels: operating voltage, clock control, and circuit size. The operating voltage is mainly related to the chip manufacturing process. Currently, a 3.3V operating voltage is selected for design using a 0.18μm CMOS process. Since the manufacturing process is beyond our control, it will not be discussed further here. For clock control, gated clock, two-phase clock pipeline, and sleep/wake-up mechanisms are mainly used. Gated clocks primarily use enable signals to control the clock signal source for each independent module and circuit, flexibly enabling and disabling the flip-flops to reduce power consumption. Two-phase clock pipelines are mainly used to improve the CPU's sequential instruction fetch speed. This method can shorten the CPU's operating time under the same bus clock and workload, reducing the CPU's duty cycle at the system level, thus lowering power consumption. The basic principle of the sleep/wake-up mechanism is to shut down temporarily unused parts of the system, even the CPU's core modules, to reduce overall system energy consumption. This MCU is designed with a full-speed working mode and two low-power sleep modes, sleep1 and sleep2, as shown in Figure 4. Both sleep modes shut down the system's main clock, but their wake-up methods and program execution modes differ. The MCU can be switched to sleep1 mode by executing the SLEP instruction. Before entering this mode, the watchdog circuit needs to be enabled to reset the watchdog or restore the working state via an external reset signal; after returning to working mode, the system restarts and resumes program execution, and previous information will be lost. This method is suitable for situations where the system has been in sleep mode for a long time and resumes operation after waking up. To enter sleep2 mode, simply set the SLPC bit in register RA. The main difference between this mode and sleep1 is that the CPU can be woken up by an interrupt signal and continue executing the program before sleep without losing any information. This method is widely used in wireless sensor networks because the MCU's operating time is much shorter than the time interval between node information acquisition and system networking operations. Therefore, the operating system can fully utilize this mode to reduce the MCU's duty cycle. In terms of circuit scale, a RISC architecture design is adopted. The CPU supports 58 reduced instructions, each instruction being a fixed 13-bit length, effectively reducing the size of the CPU core and the memory architecture. Other interface function modules in the MCU are composed of independent IPs, which can be easily customized according to requirements to achieve optimal adaptation to the embedded environment. 3. Platform Implementation 3.1 Node Implementation In this design, the self-designed MCU has been verified using an FPGA platform, and the back-end design, simulation, and fabrication were carried out using 0.18μm CMOS technology, meeting the design requirements. In the current design, the MCU occupies a 3mm×3mm silicon wafer area, but the actual logic and storage portion only occupies about 1/3. This is mainly because a large number of temporarily unused pins and test pins are retained, increasing the design perimeter. In the prototype node, the A/D conversion module uses the commercial chip MAX152. A compatible A/D circuit was also designed and fabricated along with the MCU. Mixed-signal design will be implemented in later versions to achieve system integration. 3.2 Network Construction Implementation The TinyOS embedded operating system was successfully ported to this wireless sensor network node platform, realizing the acquisition and processing of ambient temperature, operation of the RF module, and the construction of a multi-hop self-organizing network. Information data from the monitoring area is collected through the gateway node and transmitted to the monitoring terminal via the IPv6 network, realizing the basic functions of a wireless sensor network. 4. Summary This design adopts a typical wireless sensor network node architecture, developing a prototype version belonging to the general sensor platform type. System integration and miniaturization were achieved using a self-designed low-power MCU.