With the rapid development of computer technology, embedded imaging systems are widely used in office equipment, manufacturing and process design, medical, monitoring, sanitation equipment, transportation, communication, financial and banking systems, and various information appliances. An embedded imaging system refers to a dedicated computer system centered on image applications, based on computer technology, with customizable software and hardware, and strict requirements on functionality, reliability, cost, size, and power consumption. Embedded imaging systems place various stringent requirements on image display technology, necessitating the selection of suitable displays and the design of reasonable display control methods. System Hardware Design This system aims to construct an embedded, high-speed, low-power, and low-cost image display hardware platform, capable of displaying static or dynamic color images in true color. To achieve true-color and ghosting-free dynamic image display while maintaining low power consumption, a SHARP LQ057Q3DC02 color TFT-LCD is used as the display. For real-time image processing and display, a Texas Instruments (TI) high-performance DSP TMS320C6711 is used as the main processor. The data interface between the DSP and the TFT-LCD, as well as the TFT-LCD's drive control, are handled by a CPLD ispMACH4064V and a high-speed, high-capacity FIFO AL422B. The system hardware block diagram is shown in Figure 1. Figure 1 System Hardware Block Diagram 1 TFT-LCD Drive Control Hardware Design As shown in Figures 1 and 2, the CPLD drives and controls the TFT-LCD to display images by generating three clock signals: a data shift clock (CLK), a line synchronization clock (Hsync), and a frame synchronization clock (Vsync). These are then written synchronously with the clock signals through an 18-bit parallel data bus (R0～R5, G0～G5, B0～B5) to write the image data to be displayed (D0～D17). Figure 2 shows the internal structure of the LQ057Q3DC02. The hardware circuit for CPLD driving and controlling the TFT-LCD is shown in Figure 3. 2. Memory Design To minimize CPU resource consumption and allow the CPU more time for image acquisition and processing, data buffering is required during the process of the CPU outputting images to the TFT-LCD display. The CPU periodically outputs data to the buffer at high speed, and the display platform then reads the data according to the TFT-LCD's driving timing for display. The CPU's data output speed is greater than the display platform's reading speed, resulting in a high-speed write and slow read process for the buffer. The CPU outputs data periodically at a 40ms cycle, while the display platform continuously reads data for display; therefore, the buffer's write and read processes are concurrent. Figure 3 shows the hardware circuit diagram of CPLD driving and controlling the TFT-LCD. This system uses AVERLOGIC's DRAM-based high-capacity FIFO AL422B as a high-speed buffer memory. The AL422B operates at 3.3V and can withstand 5V signal voltage. Its maximum access speed is 50MHz, and its capacity is 384Kb. Since each frame of the image to be displayed is 225Kb, the AL422B can well meet the requirements of high-speed, high-capacity, and low-cost systems. However, the AL422B lacks status flags such as empty, half-full, and full, which poses a challenge to system hardware design and control. The AL422B is a synchronous FIFO with two clock signals: a read clock (RCK) and a write clock (WCK). The AL422B uses DRAM as its storage medium and requires periodic data refresh. The chip automatically selects the higher-frequency clock signal as the DRAM refresh clock, requiring at least one clock signal with a frequency not lower than 1MHz during operation. The functional block diagram of the AL422B is shown in Figure 4. Figure 4: AL422B Functional Block Diagram 3. DSP Interface Design Real-time digital image processing refers to completing specified processing on externally input digital images within a given time interval. The time delay from image input to output result must be less than the image data update rate. For an image signal with each frame being 320×240×18 bits and 25 frames per second, the data rate is 5.5 Mb/s. To achieve real-time performance, the processor's processing speed must be greater than 5.5 Mb/s, meaning the system must complete all operations on one frame of the image within 40 ms, including image acquisition, storage, transmission, processing, and display. The image acquisition rate is determined by the image sensor, such as a CCD, while the storage, transmission, processing, and display of image data depend on the CPU's performance. General-purpose devices cannot meet the system's real-time requirements; therefore, this system uses the high-performance general-purpose DSP TMS320C6711 from Texas Instruments (TI) as the main CPU. In this system, the 8-bit asynchronous mode of the TMS320C6711's EMIF port is used to periodically refresh the external synchronous FIFOAL422B along with the CPLD. The interface circuit is shown in Figure 5. Figure 5: TMS320C6711 and FIFOAL422B Interface Circuit. The DSP6711 provides the AL422B with a write reset signal (/WRST) and a write enable signal (/WE). The CPLD provides a write synchronization clock (WCK) for the AL422B based on the external memory enable signal (/CE) and write enable signal (/AWE) provided by the DSP6711. The DSP6711 writes image data into the internal memory unit of the AL422B through the data bus ED[5:0]. 4 CPLD Design This system uses ispMACH4064V (abbreviated as 4064V) as the main control logic device of the display platform. The 4064V is a new generation CPLD chip that operates at 3.3V and has I/O ports compatible with 5V TTL level. Its main performance parameters are shown in Table 1. The ispMACH4064V is the core device for implementing the timing of the logic functions of the TFT-LCD, FIFO and DSP EMIF port. In order to achieve strict synchronization between the timing functions, an external clock reference source is used to input to the ispMACH4064V. All signals inside the ispMACH4064V are based on this clock. The three key components of the TFT-LCD color digital image display platform are the DSP, FIFO, and CPLD. The DSP periodically writes image data to the FIFO via the EMIF port; the CPLD continuously reads the image data from the FIFO in parallel, driving the TFT-LCD to display dynamic or static color digital images. The DSP writes to the FIFO at a speed of up to 25MHz, the TFT-LCD refresh clock is 6MHz, and the CPLD reads from the FIFO at a speed greater than three times the TFT-LCD refresh clock, which is set to 24MHz. The timing of each component must be strictly matched for proper image display. This system uses the Lattice CPLD ispMACH4064V to generate the TFT-LCD drive timing and FIFO read timing, and works with the DSP's EMIF port to form the FIFO write timing. System timing design is a crucial and challenging aspect of digital image display technology. After power-on, the CPLD, FIFO, and TFT-LCD are reset. The DSP periodically writes image data to the FIFO, the CPLD reads the FIFO in parallel, and simultaneously drives the TFT-LCD to display the image pixel by pixel. The overall system flow is shown in Figure 6. Figure 6 shows the overall system flowchart. This system uses VHDL language to describe the behavior of the functions to be implemented by the CPLD. After syntax checking and logic synthesis of the VHDL source code using Synthesis software, functional simulation, timing simulation, pin I/O settings and allocation of ispMACH4064V are performed in the ispLEVER3.0 environment. Finally, the generated JEDEC file is written to the CPLD using a download cable to generate the actual digital logic. Performance Analysis Based on Image Processing System After image processing is completed, it needs to be displayed for observation and evaluation. The human visual system is very sensitive to color, and the colors displayed in the image must meet or exceed human resolution to avoid losing useful image information. The image display of the image processing system must achieve true color (18-bit color) display. To meet the real-time requirements of the embedded digital image processing system, the image display module should occupy as few DSP resources as possible. At the same time, true color display means greater data throughput, all of which require the image display module to have a faster processing speed. In this system, a single image frame contains 320 × 240 × 3 = 225Kb. The DSP uses an 8-bit asynchronous mode to write image data to the FIFOAL422B at a rate of 25Mb/s, requiring 9ms to write one frame. If the DSP refreshes the AL422B's image data at 40ms intervals, smooth dynamic display of true-color digital images can be achieved. This data throughput speed can well meet real-time requirements. Compared with similar products on the market: Controlling color TFT-LCDs in the domestic and international markets generally uses MCUs with TFT-LCD interfaces, such as ARM processors, or dedicated ICs, or even industrial control computers. These solutions are difficult to meet the cost and power consumption requirements of embedded systems. In the domestic market, a few companies have developed practical products using programmable devices + memory technology, with most using SRAM as the image data storage. Due to the complex read/write port switching required, these products generally use high-end programmable devices, which reduces image display quality, prevents true-color display, and hinders smooth display of dynamic images. This project achieved 18-bit true color display, 25 frames per second, and smooth display of dynamic images, all at a cost of only 40 RMB, significantly improving the product's cost-effectiveness. Conclusion This paper proposes a DSP-based color TFT-LCD digital image display solution. It employs a high-performance DSP and a novel large-capacity FIFO memory based on DRAM. A CPLD was used to implement all timing sequences for driving the TFT-LCD and interfacing with the DSP. Compared with similar products on the market, this system significantly improves image display quality and speed while reducing power consumption and cost, showing broad application prospects in embedded image systems.