With the continuous development and advancement of testing technology, low-power, high-performance DSPs can replace general-purpose microcontrollers in data acquisition and processing systems; Ethernet technology is also playing an increasingly important role in data acquisition and test measurement technologies. This paper mainly introduces the design concept and implementation of a data acquisition and processing system based on DSP and Ethernet, focusing on both software and hardware. 1. Ethernet-Based Data Acquisition and Processing System Due to the increasingly stringent testing requirements in production and research fields, the amount of data to be tested and processed is also increasing. This may require multiple testing instruments to process data simultaneously, or data exchange between these instruments. Furthermore, sometimes it is not suitable for personnel to be physically present on-site, necessitating network control. The application of Ethernet technology in a data acquisition and processing system is shown in Figure 1. Compared to fieldbuses, which are more commonly used in industrial settings, Ethernet's biggest advantages are its ease of development and low cost. By encapsulating the complex TCP/IP protocol, various network testing technologies are provided, making network testing development less complex. Simultaneously, the significant benefits of network testing enable its widespread application in the field of test automation. As a network solution for distributed testing, Ethernet undoubtedly has enormous potential. The price of Ethernet interface controllers and DSP microprocessors continues to decline, making the direct integration of Ethernet into test, acquisition and industrial I/O devices based on DSP and other embedded systems an increasingly obvious trend. Ethernet-based I/O devices embed the Ethernet interface directly into the device. Therefore, in general, when acquiring data over a network, there can be a smaller device size and more flexible installation. Compared with some other communication solutions currently used in industry, Ethernet usually requires more powerful microprocessors and memory. However, the development of network and computer technology, especially the application of DSP technology, can greatly reduce the cost in this regard. 2 Hardware Design of Data Acquisition and Processing System The system is based on the TMS320C6211 and the 10/100M adaptive Ethernet control chip MX98728EC of the TMS320C6000 (hereinafter referred to as C6000) series DSP of TI. It mainly includes three parts: ADC data acquisition, DSP data processing and Ethernet interface. Figure 2 is a block diagram of the data acquisition and processing system. (1) C6000 Series DSP The C6000 is a new generation of high-performance DSP chip launched by TI in 1997. This chip belongs to the fixed-point and floating-point compatible DSP series. The fixed-point series is TMS320C62XX, and the floating-point series is TMS320C67XX. The C6000 chip has 8 parallel processing units, divided into two identical groups. The chip's maximum clock frequency can reach 300MHz, and when the 8 processing units inside the chip run simultaneously, its maximum processing capacity can reach 2400MIPS. This data acquisition and processing system uses TMS320C6211. (2) Ethernet controller MX98728EC The MX98728EC is a general-purpose single-chip 10/100M Fast Ethernet controller. Through its host bus interface, a wide variety of applications can be implemented without or with very little external control logic. The single-chip solution can reduce the size of the circuit board and the number of chips on the board, thereby reducing the cost of the system. The MX98728EC features are as follows: ◇ 32-bit general asynchronous bus structure, supporting frequencies up to 33MHz; ◇ Monolithic solution, integrating a 10/100M TP transceiver; ◇ Optional external transceiver MII interface; ◇ Fully compatible with IEEE 802.3u protocol; ◇ Supports 16/8-bit packet buffer data width and 32/16-bit host bus data width; ◇ Separate TX and RX FIFOs, supporting full-duplex mode, independent TX and RX channels; ◇ Abundant on-chip registers to support a variety of network management functions; ◇ Supports 16/8-bit SRAM interface for packet buffers, and supports burst DMA mode for on-chip FIFOs; ◇ Automatically sets network speed and protocol with NWAY function; ◇ Optional EEPROM configuration, supporting 1Kb and 4Kb EEPROM interfaces; ◇ Supports software EEPROM interface for easy upgrade of EEPROM contents. (3) System structure ① ADC data acquisition section. CPLD1 is clocked by the DSP and its main function is to provide the address of the scan table SRAM. Data in the scan table SRAM is written by the DSP. The scan table's data output selects the analog channel to be converted from analog to digital and selects the gain of the instrumentation amplifier. The ADC uses a 14-bit LTCI416. 32 analog signals are multiplexed, selecting one signal, which is then amplified by the instrumentation amplifier before entering the ADC. The ADC's conversion clock is provided by the DSP's timer. ②DSP Data Processing Section. The 14-bit data converted by the ADC is processed by the DSP via a FIFO. The FIFO uses four CY7C425 chips in a ping-pong configuration to achieve uninterrupted sampling of analog signals. The DSP has an additional Flash memory as its program memory. Additionally, an SRAM is added as a program buffer; during offline operation, the DSP writes the program from the Flash to the SRAM and then to the DSP's internal RAM. CPLD2 is mainly used to control the FIFO's read and write operations and provides control signals for the Ethernet interface. The digital signal processing algorithms in the DSP system mainly implement filtering, sampling rate conversion, nonlinearity correction, and temperature drift correction. ③ Ethernet interface section. The Ethernet master control chip MX98728EC connects to the Ethernet via an RJ45 interface, and an SRAM is added as the Ethernet data transceiver memory. The EEPROM stores the initialization data of the Ethernet card's MAC address, I/O base address, interrupt line selection, and other configuration registers. CPLD3 controls the Ethernet chip's chip select and provides the reset signal for the Ethernet interface section by decoding the DSP's high-order address lines. The hardware design of the DSP and Ethernet interface section is shown in Figure 3. 3 Software Design of Data Acquisition and Processing System The hardware resources of the C6000 series DSP chip provide the necessary conditions for high performance. These hardware resources and development tools should be fully utilized to achieve the desired performance. On the basis of the DSP embedded system, the already packaged TCP/IP protocol stack is integrated, and network connection code is added. This is an issue that should be emphasized during software programming. Due to the complexity of the DSP system hardware and the Ethernet protocol, software programming in this system is a key challenge. In the software design of this system, the TI C6000 series DSP's real-time operating system DSP/BIOS and its real-time data exchange function RTDX (Real-Time-Data-eXchange) were adopted. DSP/BIOS, designed for the DSP application environment, provides developers with a practical and excellent real-time operating system through a series of object modules. It helps users improve software modularity, parallelism, and maintainability, thus reducing system costs and shortening development cycles. Applications running on this operating system have seen significant improvements in development time, software maintenance, and upgrades. Real-time data exchange RTDX is a new feature provided by DSP/BIOS. In many applications, the DSP is required to read data from or output data to the host in real time without stopping. Because the software structure of this system is relatively complex and involves many algorithms, a modular, top-down, and progressively refined structured programming approach should be adopted. This approach can save software workload and improve work efficiency. Figure 4 shows a simplified flowchart of the main data acquisition and processing program. Conclusion Practice has proven that the DSP-based and Ethernet-based data acquisition and processing system designed according to the above scheme can effectively realize the function of acquiring and processing analog signals. Based on this, it can also serve as an important debugging tool in the development of network test platforms based on DSP embedded systems and Ethernet, thereby accelerating the development process of integrating Ethernet into test, acquisition, and industrial I/O instruments.