The MPC755 is a high-performance G3 generation product in the PowerPC series of microprocessors developed by Freescale. This paper introduces the architecture, main chips, address space allocation, implementation challenges, debugging methods, and startup process of an embedded computer system based on the MPC755. This embedded system boasts superior processing power, with a core processing capability of up to 733 MIPS, and can be used for voice processing, routers, wireless access, VoIP, softswitches, and more. With the advent of the information age, embedded systems are increasingly widely used in communication, and the demand for bandwidth is rising. New services require embedded systems to have stronger processing capabilities. This paper uses the MPC755 as its core to build a powerful, highly modular, real-time, and highly scalable embedded computer system, which can be used in voice processing, routers, wireless access, VoIP, softswitches, and many other applications. Because the MPC755 has advantages such as parallel execution of multiple instructions, fast execution of simple instructions, and pipelined operation, this system boasts superior processing power, with a core processing capability of up to 733 MIPS. The MPC107 expands its communication protocol processing interfaces through the main/PCI bridge, meeting the requirements of various RTOS (Real-Time Operating Systems, such as VxWorks, Embedded Linux, etc.) for their operating platforms. Figure 1: MPC755 Block Diagram. The MPC755 processor is a 32-bit superscalar microprocessor that follows the PowerPC processor architecture and has the same instruction set as PowerPC. The chip integrates 6 independent execution units (2 integer units, 1 load/store unit, 1 double-precision floating-point unit, 1 system register unit, and 1 jump processing unit), which can execute up to 6 instructions simultaneously in one clock cycle. The MPC755 embeds an independent 32KB instruction and data cache, as well as an instruction and data memory management unit (MMU). The L2 cache control unit can connect up to 1MB of SRAM externally for use as a secondary cache. The bus interface unit leads out a 60X bus, which can connect to devices with a 60X bus. When the core operates at 400MHz, the performance reaches 733MIPS. The MPC755 also includes a performance monitor, a JTAG debug interface conforming to the IEEE 1149.1 standard, and a temperature management unit (see Figure 1 for the MPC755 functional structure). The MPC755 is backward compatible in pin definitions and software code, with a core voltage of 2.0V and selectable I/O voltages of 3.3V/1.8V. The maximum frequency of the MPC755 core is 400MHz. The system clock is input through the SYSCLK0 pin, multiplied by the PLL circuit to generate the core clock, i.e., the main frequency. The configuration value of pins PLL_CFG[0:3] at system power-on (0b'1010 in this design) determines the multiplication factor. System Overall Design Figure 2 is a system block diagram of an embedded computer based on the MPC755. As shown in the figure, the interface expansion of the MPC755 mainly relies on the main/PCI bridge—MPC107. The MPC755 itself only has an external L2 cache to improve system performance. All other interfaces are derived from the MPC107, including a serial port, a 10M/100M adaptive Ethernet port, and an I2C port. The serial and Ethernet ports meet the requirements of various RTOS operating platforms and provide hardware support for the two main debugging methods of embedded systems (serial debugging and Ethernet debugging), making application development quite easy. The PMC slot provides strong field scalability, meeting diverse application needs. Figure 2: System block diagram based on MPC755. 1. MPC107 The MPC107 is a high-performance, high-bandwidth PCI bridge chip developed by Freescale. Figure 3 shows the basic structure of the MPC107. One side of the MPC107 is a 60X bus interface with a selectable 32-bit/64-bit bus width and a maximum frequency of 100MHz; the other side is a PCI bus interface. The chip integrates a memory controller, DMA controller, programmable interrupt controller, four timers, an I2C controller, message unit (I2O), PCI arbiter, watchdog circuit, dynamic power management unit, PCI bus performance monitoring unit, and JTAG interface. The memory controller has 12 chip select spaces, including 8 RAM chip select spaces, CS[0:7]. The timing of each chip select space is programmable, supporting FPM DRAM, EDO DRAM or SDRAM, with a maximum external RAM capacity of 1GB. The other 4 are ROM chip select spaces, RCS[0:3], supporting 8-bit, 32-bit, and 64-bit interface widths, with a maximum external ROM capacity of 144MB. 2. Memory: This system expands the CS0 space with 128MB of SDRAM, using five 256M-bit (16M (16-bit) SDRAM chips, one of which is used for ECC, and the other four are used as system memory. The Flash memory chosen is an Intel 28F016S3, 2MB. Because the system must read the boot code from the device on RCS0 during startup, the Flash chip select is connected to RCS0. The At24C04 is a 512-byte EEPROM, connected to the MPC107 via the I2C bus, used to store system information such as product name, version number, and network port physical address. Figure 3: MPC107 Block Diagram. The secondary cache uses IDT's IDT71V35761, 128K (36-bit) per chip, two chips in total, combined to form 128K×72-bit, of which 64 bits are data lines and the other 8 bits are parity signals. The chip's maximum frequency is 200MHz. The use of the secondary cache greatly improves system performance, making the MPC755 even more powerful. 3. Serial Port: TL16C550 is an RS-232 serial port control chip, connected in RCS1 space, and MAX3221 is a level conversion chip. The serial port's operating mode is determined by software, and it can work in interrupt mode or polling mode. During debugging, the serial port is used to output debugging information and receive external commands. In practical applications, the serial port can serve as a communication window between the system and the user, allowing the user to monitor or change the system's operation. 4. In this system, the PCI device uses the MPC107 internal arbiter, and the bus operates at 33MHz. The network port chip selected is the Intel 82559, a 10M/100M adaptive network port chip with a PCI interface that integrates the physical and data link layers, reducing board space and trace count. The transformer used is the Pulse H1012. The network port can operate in full-duplex or half-duplex mode. Additionally, the PCI1410A is an interface chip connecting the PCI bus and the CF card. CF cards have advantages such as portability, ease of upgrade, large storage capacity, and good shock resistance. In this design, the CF card is mainly used to store application software and back up user data. Moreover, in future system maintenance and software upgrades, technicians only need to replace the CF card or upgrade the software within it, which is very convenient. The design uses a SanDisk SDCFB-64-101 CF card with a 64MB capacity and geometric dimensions of 36.4mm × 42.8mm × 3mm. Table 1: Address Space Allocation. The PMC slot is used to expand PCI cards and increase system functionality. For example, if the system needs to add a network port, simply insert a network card with a PMC interface into the PMC slot. 5. Clock: The M41T81 is a clock chip manufactured by STMicroelectronics. In this design, it provides a clock for the system because in many applications such as telecommunications and networking, the system must provide time information. The M41T81 has an I2C interface and two power supply modes: when the system is powered on, it is powered by the 3.3V power supply on the circuit board; when the system is powered off, it automatically switches to external battery power. The current drawn by the battery is very small, only 1 A. Address Space Allocation : In PCI master mode, the MPC107 supports two address space allocation schemes: Map A and Map B. In PCI slave mode, the MPC107 only supports Map B. The choice of address allocation scheme is determined by the high or low state of the SDBA0 pin during power-on; if it is high, Map B is selected; otherwise, Map A is selected. In this system, the MPC107 operates in PCI master mode, and Map A is selected. Map B address space allocation scheme. In the Map B address space allocation scheme, the entire 32-bit (4GB) address space is divided into four main blocks: local storage space, PCI storage space, PCI I/O space, and system ROM space, as shown in Table 1. In this system, the base address of 128MB SDRAM is 0000_0000, the base address of 2MB Flash is FFE0_0000, the base address of the serial port control chip TL16C550 is 7C00_0000, and the access address of the 64M CF card is 8000_0000. Design Key 1. The clock signal is a key component of this design. The entire system has only one clock input: OSC_IN, 33MHz, which is input to the MPC107. After passing through the MPC107's FO buffer, it generates five synchronous PCI clock signals. Three of these PCI clocks are sent to PCI devices, one is reserved, and the remaining PCI clock serves as the system clock (PCISYNC_OUT), which is sent to the PLL and DLL (Phase-Locked Loop) modules. After phase-locking and frequency multiplication, it generates the CPU clock (CPU_CLK0), four SDRAM clocks (SDRAM_CLKx), and one feedback clock (SDRAM_SYNC). CPU_CLK0 is then sent to the MPC755. Table 2: Important Routing Diagram. The MPC107's DLL module is similar to a PLL, but it can divide a clock cycle into 128 discrete intervals. During PCB routing, the SDRAM clock traces are of equal length. The DLL detects the delay of the SDRAM_SYNC clock from output to input; this delay is equivalent to the SDRAM_CLK delay. By adjusting the SDRAM_SYNC clock delay, the SDRAM_CLK clock delay can be easily increased or decreased. Generally, a trace length of 16.5cm corresponds to a delay of 1000ps. In this design, the trace lengths of CPU_CLK0, SDRAM_SYNC, and SDRAM_CLK are equal. The trace length from PCISYNC_OUT to PCISYNC_IN is equal to the PCICLK trace length. The MPC755 obtains the core clock frequency by multiplying the CPU_CLK0 clock. The L2 cache clock is allocated by the MPC755 based on the core clock frequency, and the division factor is determined by the L2CLK bit in the L2CR register, which can be 1, 1.5, 2, 2.5, or 3 (this system uses 2.5). Generally, the choice of the division factor depends on the performance of the external cache, the MPC755's core operating frequency, and the adjustment capability of the DLL. The minimum operating frequency of the L2 cache is 80MHz. The divided clock is adjusted by the on-chip DLL circuit and then sent to the L2 cache. However, L2SYNC_OUT, as a feedback clock, is also input to L2SYNC_IN, and the return path length must be half the length of the L2CLK_OUTA trace. This ensures that the rising edge of the clock signal input to the L2 cache is aligned with the rising edge of the clock signal from the L2 interface. 2. The external circuitry of the PLL for the MPC107 must be placed as close to the MPC107 as possible during high-speed routing. The traces between the 82559 Ethernet chip and the H1012 transformer should be as short as possible, and the pair of input signals and the pair of output signals for the Ethernet port should use differential routing. The data and address lines connecting the MPC755 and the L2 cache should be as equal in length as possible. Because two SRAM chips need to be connected, a "Y" routing method is used. Special attention also needs to be paid to the address, data, and control lines of the SDRAM and L2 cache. As shown in Table 2, all high-speed traces, including PCI traces, have undergone impedance matching control. System Startup and Debugging Table 3: Startup Configuration Pins and Their Meanings When the signal #HRESET is low, the MPC107 reads the configuration pins to determine the operating state. These configuration pins are multiplexed; however, during power-up, they only function as configuration pins. The meanings of the key configuration pins are shown in Table 3. The system's hardware debugging utilized Windriver's EST7xx series emulator. One end of the emulator connected to the PC, and the other end to the MPC755's JTAG interface. Even if modules like the SDRAM malfunctioned, the emulator could access the internal registers of the MPC755 and MPC107 to help diagnose the faults in the SDRAM and other devices. First, the PowerPC core and external SDRAM were debugged. Once they were functioning correctly, an RTOS could be downloaded via the emulator to assist in hardware debugging. For this purpose, Windriver's embedded real-time operating system, VxWorks, and its integrated development tool Tornado were chosen. Next, the serial port was debugged, as it is relatively simple. If the serial port functioned correctly, the emulator could be discontinued, and tools provided by Tornado, such as WDB, could be used to establish communication between the circuit board and the PC via the serial cable to continue debugging other modules. The main workload for debugging was on the MPC107, not the MPC755. After debugging, the correct boot code is burned into the Flash memory, and VxWorks and application software are burned into the CF card. Because the base address of the interrupt entry point during boot is 0xFFF00000, while the interrupt vector offset address for PowerPC processor boot is 0x100, the boot code must be burned into the Flash memory at address 0xFFF00100. After system power-on or hard reset, the MPC755 automatically reads instructions from this address and executes them in the following steps: PowerPC kernel initialization; disabling all interrupts; initializing SDRAM; initializing the MPC755's internal cache; initializing the L2 cache; initializing the PCI interface; initializing the CF card; reading VxWorks and application software from the CF card into SDRAM; running VxWorks; initializing the serial port; initializing I2C and reading the MAC address from the AT24C04; initializing the network port; enabling interrupts; running the application software. The initial program in the Bootrom is written in PowerPC assembly language. This part of the program completes the most basic initialization of the system, the most important of which is the PowerPC kernel and SDRAM, so that SDRAM can be used as soon as possible, so that subsequent initialization work can be performed using a program written in C language.