Abstract: This paper introduces the characteristics of the CAN (Controller Area Network) bus, presents the circuit principle of the intelligent node in the CAN bus system, and provides a development program written in C51 language to facilitate user learning and mastery. Keywords: CAN bus; SJAl000; intelligent node; AT89C51 1 Introduction CAN (Controller Area Network) is a fieldbus mainly used for the detection and control of various devices. The CAN bus is a serial data communication protocol developed by Bosch in Germany in the early 1980s to solve the data exchange between numerous control and testing instruments in automobiles. It is a multi-master bus, widely used in both high-speed networks and low-cost node systems. Due to the adoption of many new technologies and unique designs, compared with general communication buses, the CAN bus data communication has outstanding reliability, real-time performance, and flexibility. Its main characteristics are as follows: ● Flexible communication mode: It can work in multi-master mode. Any node on the network can actively send information to other nodes on the network at any time, without master-slave distinction. ● CAN nodes only need to filter the message identifier to send and receive data in point-to-point, point-to-multipoint, and global broadcast modes. Nodes can be divided into different priorities, which can be set via message identifiers. High-priority data can be transmitted within a maximum of 134μs, meeting various real-time requirements. ● The CAN bus communication format uses a short frame format, with each frame typically containing 8 bytes. This meets the requirements of control commands, operating status, and test data in general industrial applications. Furthermore, the 8-byte frame does not occupy excessive bus time, ensuring real-time communication. ● It employs non-destructive bus arbitration technology. When multiple nodes simultaneously send information to the bus and a conflict occurs, lower-priority nodes will actively withdraw from data transmission, while higher-priority nodes can continue transmitting data unaffected. This significantly saves bus conflict arbitration time and prevents network paralysis under heavy network load. ● The maximum direct communication distance is up to 10 km (at a rate below 5 kb/s), and the maximum communication rate is up to 1 Mb/s (at which point the maximum distance is 40 m). Up to 110 nodes can be connected, and the communication medium can be twisted-pair cable, coaxial cable, or optical fiber. ● The CAN bus employs CRC checking and provides corresponding error handling functions to ensure the reliability of data communication. Its nodes have an automatic output shutdown function in case of severe errors, ensuring that the operation of other nodes on the bus is not affected. 2. CAN Bus System Structure Since the CAN bus operates in a multi-master mode, it has a different topology than a DCS (Distributed Control System). Its control system consists of a computer and intelligent nodes, as shown in Figure 1. The biggest feature of this system is that all nodes can be connected to the bus on an equal footing. A bus node typically includes at least three parts: a microcontroller that controls the node's tasks, a bus controller, and a bus driver. This article mainly introduces the simple design of a CAN bus intelligent node. The intelligent node consists of an 89C51 microcontroller, an SJA1000 bus controller, an 82C250 bus driver, and a PC. In practical applications, different sensors can be connected to complete data acquisition and transmission. 3. Hardware Circuit Design The intelligent node of the CAN bus system designed by the author uses the Intel AT89C51 microcontroller as the node's microprocessor. The AT89C51 has 64KB of address space. Since it doesn't have a built-in CAN controller, an external CAN controller and CAN driver are needed to achieve communication with the CAN bus. This design uses the SJAl000 CAN bus communication controller and the AT82C250 bus driver. The hardware circuit of the intelligent node in the CAN bus system is shown in Figure 2. As can be seen from Figure 2, the hardware circuit mainly consists of an AT89C51, SJAl000, AT82C250, a 6N137 high-speed optocoupler, and a MAX202 level converter. The AT89C51 is responsible for initializing the SJAl000 and controlling it to perform communication tasks such as data reception and transmission. The MAX202 is used for mutual conversion between TTL and RS232 levels, and can display the received data on the PC. The SJAl000's ADO-AD7 is connected to the AT89C51's P0 port, and CS is connected to the AT89C51's P2.7 port. When P2.7 is 0, the CPU can select SJA1000 as an external memory address, and the CPU can perform corresponding read/write operations on SJA1000 through these addresses. The RD, WR, and ALE pins of SJA1000 are connected to the corresponding pins of the AT89C51, and the INT pin of SJA1000 is connected to the INT1 pin of the AT89C51. The AT89C51 can also access SJA1000 via interrupts. To enhance the anti-interference capability of the bus nodes, the TX0 and RX0 pins of SJA1000 are not directly connected to the TXD and RXD pins of the 82C250, but are connected to the AT82C250 through a 6N137. This effectively achieves electrical isolation between nodes on the bus. However, the two power supplies VCC and VDD used in the optocoupler circuit must be isolated. Complete power supply isolation can be achieved using a low-power power isolation module. Although this increases the complexity of the interface circuit, it improves the stability and safety of the nodes. The interface between the AT82C250 and the bus also incorporates certain safety and anti-interference measures. The CANH and CANL pins of the AT82C250 are each connected to the bus via a 5Ω resistor. These resistors provide current limiting, protecting the AT82C250 from overcurrent surges. Two 30pF capacitors are connected in parallel between CANH and CANL and ground to filter high-frequency interference on the bus and provide some electromagnetic radiation protection. Additionally, a surge protector is connected between each of the two CAN bus inputs and ground. When transient interference occurs between the two inputs and ground, the surge protector's discharge provides some protection. A slope resistor is connected to the RS pin of the AT82C250; its value can be adjusted according to the bus communication speed, typically between 16 kΩ and 140 kΩ. 4. Software Design 4.1 Network Communication Rules The CAN bus operates in a multi-master mode. Any node on the network can actively send information to other nodes at any time without master-slave distinction, offering flexible communication. To prevent bus collisions, the CAN bus employs a non-destructive bus arbitration technique. Each node is assigned a different priority as needed, identified by an identifier (ID). A smaller ID value indicates a higher priority. Nodes on the bus can communicate with each other in real time. When a node needs to receive data from another node, it simply sets its code register to match the identifier of the other node. If the identifier and code register settings are inconsistent, the data sent by the node will be ignored. 4.2 SJAl000 Operating Mode Settings The SJAl000 has two operating modes: reset mode and working mode. In reset mode, the receive code, receive mask, bus timing registers 0 and 1, and output control register can be configured. These registers are typically configured during CAN initialization, and their values ​​remain unchanged after CAN enters working mode. Data can be sent and received in working mode. It is particularly important to note that a hardware reset or controller disconnection will automatically enter reset mode, preventing normal CAN communication. Therefore, monitoring the reset bit is necessary. When a hardware reset or controller disconnection occurs and the system enters reset mode, the reset bit must be set to 0 and the system must enter working mode so that CAN can transmit and receive normally. 4.3 The software design of the system based on C language is as follows: After the system powers on, the AT89C51 and SJAl000 are initialized to determine the operating frequency, baud rate, output characteristics, etc. Any intelligent node can use polling to obtain the required data from the CAN bus through SJAl000 and transmit the data to the PC for display. Simultaneously, it can send data to the bus for other intelligent nodes to receive and display. The following is the specific implementation program. The above is the program used for the experiment. reg51.h is a library function specifically written for the AT89C52 main controller; it is readily available in Keil software and can be included using the #include statement. intrins.h prepares for future calls to the empty function _nop_(), and it includes NOP statements similar to assembly language. CAN_TOUWENJIAN.h is a header file used to define relevant registers. The `Tx_DATA_CAN()` function is used to send data to the bus, the `REC_DATA_CAN()` function is used to receive data from the bus, and `SERIAL()` is used for communication between the PC and the intelligent node. Due to space limitations, the sending and receiving subroutines are not specifically provided. 5. Conclusion During the development and experimentation of the CAN bus, the author mastered the design of CAN bus intelligent nodes and applied it in practice. Application results demonstrate that the CAN bus has the following advantages: flexible networking and strong scalability; automatic error identification, simplifying communication operations; and the ability to determine priority based on data content, solving real-time communication issues. Furthermore, CAN networks have been applied in numerous industrial control systems, especially in applications with high transmission rates and high requirements for real-time performance and reliability, where the CAN bus has broad application prospects. This paper originates from the research group "Research on Improvement of Signal Information Transmission in a Certain Control System," led by Professor Liu Yonghong, with Associate Professor Zhang Wenhong as the deputy leader, and Associate Professor Huang Chen, Lecturer Zhao Yong, and graduate student Li Jingang as key participants.