Abstract: SOPC technology, which integrates the processor core into an FPGA chip, is an embedded system solution with unique advantages. In the development of an embedded Ethernet network terminal, the SOPCBuilder design tool of the Quartus II software platform was used to integrate the Nios soft-core processor, Ethernet chip control circuit, control circuits of other peripheral devices, and user logic circuits onto a single Cyclone programmable logic chip. Running the μC/OS II embedded operating system, LWIP network communication protocol, and application software on this network terminal enables various network communication functions. Keywords: Ethernet; network terminal; system-on-a-programmable chip 1 Introduction In recent years, with the rapid development of the Internet, Ethernet has become the most widely used data access network due to its broadband, strong scalability, and flexible networking. Ethernet network terminal equipment is an important component of the network, serving as the protocol interface and working platform for information exchange between the network and external networks. Embedded Ethernet network terminal equipment adopts embedded processor technology, uses an embedded operating system, and has embedded network interfaces and network communication protocols, allowing direct access to Ethernet. Embedded network terminal devices are increasingly widely used in communication and industrial control fields due to their advantages such as low cost, small size, high reliability, low power consumption, and strong environmental adaptability. This article mainly introduces the design and practice of building an embedded Ethernet network terminal using SOPC technology. An embedded Ethernet network terminal based on SOPC technology can provide a basic working platform for various networking applications. Unlike currently popular embedded processors such as ARM-based processors and PowerPC series processors, SOPC technology embeds the processor as a "core" into an FPGA chip, implementing system functions on a programmable chip. There are two types of embeddable processor cores: hard cores and soft cores. Soft cores are more suitable for applications in differentiated products in small-batch production due to their low cost, high reconfigurability, flexible functions, and wide range of applicable FPGA chips. FPGAs use hardware technology to process signals and can be repeatedly programmed in software, balancing speed and flexibility, and real-time performance can be accurately predicted and simulated. A significant advantage of FPGA chips is their powerful hardware parallel processing capability, which is not limited by the processor architecture but only depends on the chip's physical resources. With the advancement of deep submicron semiconductor technology, the capacity of logic gates and on-chip memory in a single FPGA chip has developed rapidly, and programmable logic chips with millions of gates have become commonplace. Therefore, in multi-channel signal processing with general algorithmic complexity (typically voice communication and industrial control), FPGAs are more capable than DSPs, and this advantage becomes more pronounced as the number of parallel processing channels increases. Nios is a soft-core processor developed by Altera. By applying SOPC technology to integrate Nios into an FPGA chip, the network terminal no longer needs an external processor; a single FPGA chip can achieve the functions previously requiring an FPGA + CPU. 2. Overall Design of the Network Terminal The hardware and firmware of the embedded Ethernet network terminal based on SOPC technology consists of an FPGA chip with a Nios soft-core CPU, external data storage FlashRAM and SDRAM, an analog signal processing module with AD and DA conversion circuits, an RS-232 serial communication circuit, an Ethernet network module and RJ45 and JTAG interface circuits, as shown in Figure 1. Power supply and configuration circuits are also included, but are omitted here. Figure 1 shows a schematic diagram of the network terminal circuit module. In Figure 1, the FPGA chip used is the Altera Cyclone series chip EP1C6Q240C8. This chip is fabricated using a 0.13μm all-copper 1.5V SRAM process, featuring 5980 logic elements (LEs), 92160 RAM bits, two digital phase-locked loops (PLLs), and a 240-pin PQFP package. The program memory uses the AMD Flash RAM chip AM29LV017D, with a storage capacity of 2MByte and a write/erase cycle of up to 1 million. The data memory uses the Micron SDRAM chip MT48LC4M32B2, with a storage capacity of 16MByte and an access speed of 5.5ns. The use of a larger capacity data memory is primarily to reserve space for future testing and running of various embedded operating systems. The Ethernet interface chip used is the CS8900A. This chip, manufactured by Cirrus Logic, is a local area network (LAN) signal processing chip. It integrates on-chip RAM, and its analog front-end includes a Manchester codec, clock recovery circuitry, a 10BASE-T transceiver, filters, and an AUI port. The CS8900A's MAC (Media Access Control) engine is responsible for sending and receiving Ethernet data frames, detecting and handling collisions, generating and detecting frame preambles, and automatically generating and verifying CRC (Cyclic Redundancy Check) codes. The chip conforms to the IEEE 802.3 Ethernet standard at the network physical layer and supports full-duplex operation. The A/D and D/A converters use Analog Devices' AD73311L chip. The AD73311L has one 16-bit A/D conversion channel and one 16-bit D/A conversion channel. The gains of the A/D and D/A conversion channels are programmable in the ranges of 38dB and 21dB, respectively, and each channel provides a signal-to-noise ratio of 70dB across the audio frequency band. The sampling frequency is 8kHz to 64kHz, programmable, and the sampling word length is 16 bits. The AD73311L was chosen because it can be used for general analog signal A/D and D/A conversion, and also meets the front-end processing requirements for voice signals, facilitating future VoIP functionality testing. The JTAG interface is used to download configuration files from the PC to the FPGA chip and debug the system, while the serial port is used to connect to the PC for system software debugging and to transmit information to external devices in network applications. The terminal's software mainly consists of the embedded operating system μC/OS-II, the network protocol LWIP, and application software. An embedded operating system is a real-time operating system that supports embedded applications, typically including hardware-related low-level driver software, a system kernel, device driver interfaces, and communication protocols. Compared to PC operating systems, embedded operating systems have significant advantages in real-time efficiency, hardware dependency, software solidification, and application specialization. Currently, various major embedded operating systems (such as Windows CE, VxWorks, μC-Linux, μC/OSII, etc.) support various types of peripheral hardware devices and multiple communication protocols to varying degrees, providing numerous means to implement peripheral hardware drivers. A complete operating system supports many communication protocols; by using an operating system, these protocols can be directly called to achieve communication, avoiding excessive low-level programming that consumes time and effort and reduces errors. In this network terminal, μC/OSII was chosen as the embedded operating system. μC/OSII is a relatively mature and free embedded operating system, suitable for small control systems, and features high execution efficiency, small footprint, and excellent real-time performance. Its disadvantage is that its support for complex applications such as file systems and networks is inferior to commercial embedded operating systems. For network communication software, LWIP was chosen to implement TCP/IP communication. LWIP is an open-source and free TCP/IP protocol stack developed by Adam Dunkels and other scholars at the Swiss Federal Institute for Computer Science. LWIP can run on an operating system or independently. LWIP provides an application programming interface similar to Berkeley Sockets, and code written using it has excellent compatibility, easily ported to other common operating systems with minor modifications. Because the μC/OS II operating system lacks a built-in TCP/IP protocol stack, this network terminal ported LWIP to the μC/OS II operating system, making it a network module of the operating system, thus placing network communication under the control of μC/OS II. 3. SOPC Development Process Developing systems using soft-core processors has its unique development process. This paper uses the Nios CPU, a soft-core processor from Altera Corporation, as an example, and primarily uses Altera's design software. These software tools include Quartus II, SOPC Builder, and GNU Pro Toolkit. Quartus II is Altera's FPGA design software, featuring design input, synthesis, simulation, delay analysis, compilation, file download, and device configuration functions. SOPC Builder is used for the logic design of system modules on the Quartus II design platform. SOPC Builder can be used for system module hardware design and low-level software generation. When designing hardware modules, SOPC Builder provides a graphical configuration interface with IP modules for some commonly used peripherals, such as SDRAM, FlashRAM, UART, Ethernet Interface, Intervaltimer, and Parallel I/O. These pre-developed functional modules, already integrated into the SOPC Builder environment, are called components. These components can be viewed on the left side of the SOPC Builder graphical interface. Users can also add their own peripheral design files using "Interface to User Logic," or directly add peripheral interfaces. Acceptable peripheral design files include .vhd or .v files written in VHDL or Verilog HDL, EDIF files generated by MAX+plusII, or circuit diagrams imported using Quartus II. SOPC Builder can perform system configuration and generation. System configuration includes settings for peripherals, bootloader, interrupt vector table, system boot address, etc. Application software design is performed in the Cygwin environment using the GNU Pro toolkit. This toolkit includes commands for compiling and downloading software, as well as operations on common files, making it easy for developers familiar with Cygwin and Linux to use. The entire SOPC development process is shown in Figure 2. When designing the system, first create a new project in Quartus II, and then design according to the process shown in Figure 2. The first step is to determine the CPU, setting whether it is 16-bit or 32-bit, and whether to add hardware multiplication instructions, etc. This step is performed in "Configure Processor". The second step is to select peripheral devices such as UART, SDRAM, FlashRAM, Timer, and general-purpose I/O, and add user circuit modules to the system, also in this step. The third step is generation, which generates hardware components described in HDL language and an SDK for software development. These three steps are all performed in SOPC Builder. The next steps are divided into hardware design and software design. In hardware design, the on-chip system design and addition of user circuits are performed according to the process shown on the left side of Figure 2, including circuit connections, chip selection, pin settings, etc. After system synthesis, a .sof file is generated, and functional simulation and timing simulation analysis of the system hardware can be performed as needed. In terms of software design, the software design, compilation, and linking are carried out according to the process shown on the right side of Figure 2. The working environment for this step is mainly the SOPC Builder software development environment, also known as Cygnus. Compiling the software code uses nios-build (abbreviated as nb), srec-flash is used to generate code that boots from Flash RAM, and downloading the software to the system uses nios-run (abbreviated as nr). The hardware and software design processes are finally combined, and the designed circuit configuration file .sof is downloaded to the Altera FPGA via JTAG for debugging. 4. Design Considerations for Embedded Network Terminals 4.1 Design and Application of Nios Processor This network terminal uses a 32-bit processor. The Nios soft-core processor is configured into the FPGA chip using the SOPC Builder software on the Quartus II design platform. The Nios soft-core can be configured as a 16-bit or 32-bit processor as needed, with a 16-bit instruction set. Generally, a system built with a 16-bit processor is faster than a 32-bit system, but a 32-bit processor can manage more resources than a 16-bit system. The bit width of the data bus, address bus, registers, and arithmetic logic unit (ALU) can be configured to 16 or 32 bits as needed. The number of registers is also configurable. The Nios CPU architecture has one general-purpose register set, 10 control registers, one program register, and one K register. In a 32-bit Nios CPU, each general-purpose register has a bit width of 32. The number of registers in the general-purpose register set can be set to 128, 256, or 512 as needed. At any given time, Nios can directly access (without changing the CWP) 32 general-purpose registers, called the register window. The number of registers in the set is called the length of the window, also known as the size of the register window, with a value of 32. The register window has four parts. The bottom 8 registers are called global registers, namely %r0 to %r7, also known as %g0 to %g7; global registers do not change with the position of the register window, and the CPU can access them at any time. The remaining 24 registers are accessed through the current register window. The top eight registers are called input registers, followed by local registers, and the eight registers between the local and global registers are the output registers. 4.2 FPGA On-Chip System The on-chip system includes the CPU, a bus system closely connected to the CPU, and peripheral hardware control circuits. SOPC Builder allows selection and configuration of on-chip system modules, as well as allocation and modification of system addresses and interrupt numbers for each component. SOPC Builder designed a special bus for Nios—the Avalon bus. Avalon is a simple bus structure that defines the interface between master and slave components and the timing of inter-component communication. The Avalon bus is composed of active logic units, replacing the metal traces on traditional PCB boards. SOPC Builder generates an Avalon bus .vhd file based on the system configuration, which is then synthesized into the on-chip bus structure by Quartus II. The on-chip system settings for this network terminal are shown in Figure 3, which is the component setting interface of the SOPC Builder software. The starting address and interrupt number can be directly modified to appropriate values ​​in this interface. Figure 3 shows the system address and interrupt number allocation. Besides setting specific components, the system's boot address, interrupt vector table, program memory, data memory, main serial port, and auxiliary serial port also need to be set, as shown in Figure 4. These settings are closely related to the linking process of the software object files. SOPC Builder will generate the relevant files in the subdirectories lib and inc of the cpu-sdk directory based on these settings. Figure 4 shows the system boot address, program memory, data memory, etc. 4.3 Network Interface Control Settings The Ethernet interface chip CS8900A operates in I/O mode. The functions of the network terminal interface circuit and the reading of status information can be set by operating the chip's registers. The main registers of CS8900A are: LineCTL: determines the basic configuration and physical interface of CS8900A, set the initial value to 00D3H, and select the physical interface as 10BASE-T. RxCTL: controls CS8900A to receive specific datagrams, set the initial value of RxCTL to 0D05H, and receive broadcast datagrams on the network or correct datagrams with the same destination address as the local physical address. RxCFG: Controls the CS8900A to trigger a receive interrupt upon receiving a specific datagram. RxCFG can be set to 0103H to generate a receive interrupt when a correct datagram is received. BusCTL: Controls the chip's I/O interface operation. Setting the initial value to 8017H enables the CS8900A's global interrupt control bit. ISQ: Interrupt status register, internally mapping the contents of the receive status register and transmit interrupt register. Port0: The CPU transmits data through Port0 during transmission and reception. TxCMD: Transmit control register. If 00C0H is written, the network card chip will start transmitting data after all data has been written. TxLength: Transmit data length register. When transmitting data, the transmit data length is written first, and then the data is written to the chip through Port0. Upon system power-up, the CS8900A is first initialized by writing registers LineCTL, RxCTL, RxCFG, and BusCTL. When transmitting data, the control register TxCMD is written, and the transmit data length is written to TxLength. Then, the data is sequentially written to Port0, and the data can be transmitted. When data is received, the CS8900A will trigger an interrupt, in which data can be received and processed. 4.4 The AD/DA circuit network terminal can acquire digital and analog signals. Digital signals can be directly sent to the FPGA for processing, while analog signals need to be converted to digital signals by the AD73311L chip before being sent to the FPGA. The AD73311L is initialized before operation, with settings such as sampling rate and input/output gain, and then put into data transmission mode for normal operation. The AD73311L communicates with the FPGA chip serially, reducing the number of interconnections between chips. Internally, serial/parallel and parallel/serial conversions are required within the FPGA. To enable the AD73311L to be controlled by the CPU, a dedicated AD/DA component is added in SOPC Builder using the "Interface to User Logic" function, and the corresponding pins are connected to external circuits. 4.5 Software Composition and the software development tools配套 with the Nios CPU can be used in Cygwin. Cygwin is a Linux-like environment developed by Red Hat that runs on the Windows platform. Therefore, the process of writing, compiling, and linking programs for Nios is very similar to that under general Linux. Logically, the software can be divided into five parts, with the startup program Germ Monitor forming a separate part, provided by Altera. The remaining four parts are organized, written, and modified by the designers. The structure based on SOPC technology is shown in Figure 5. Figure 5: Package Structure Diagram. The process of obtaining the final executable file from the source code is controlled by a special text file called Makefile. The Makefile guides the compilation process from source files to object files and the linking process from object files to executable files; therefore, it can be considered the management file for the entire software program. The Makefile uses a text file format and works with the Make program to create the final application. The Makefile defines the dependencies between target files and dependent files, as well as the commands that the target files should execute based on the dependent files. The entire package contains four Makefile files. The Makefile for the μC/OSⅡ operating system is located in the librtos32 directory and is responsible for compiling the operating system code, ultimately producing the operating system support library file librtos32.a. The Makefile for the lwIP network communication protocol is located in the src directory. It is responsible for compiling the network support code and ultimately generating the library file liblwip.a. The Makefile for the network terminal application software is located in the top-level directory UCOSII-lwip. It guides the compiler to generate the library file liblwipapp.a. The main Makefile, also located in the top-level directory, is used to generate the executable program that will be downloaded to the circuit board. 4.6 System Startup The network terminal uses Germ Monitor, a monitoring program included in the Nios development kit, with slight modifications. It is a small shell program configured in the FPGA's on-chip ROM, allowing the system to boot before the operating system. During hardware configuration, the Nios boot address is set to the on-chip ROM address, and the system will run from that address upon power-on reset. Other boot methods can also be used, such as directly driving from Flash RAM. Hardware initialization and peripheral device status settings can be performed within the boot program. After initialization, Germ Monitor loads the application program from Flash RAM into SDRAM and then jumps to the application program, allowing the Ethernet network terminal to run its various functions as designed. 5. Conclusion After the above design and debugging, the embedded Ethernet terminal can function normally. Connecting two such terminal circuit boards to a local area network with a network cable, setting their respective IP addresses, and running the application software enables various functions. Interconnecting the serial port of the PC and the serial port of the network terminal allows monitoring of the terminal's operating status from the PC. Experiments successfully implemented VoIP voice communication and Telnet data communication between the two terminals. Due to space limitations, this design application will be discussed in another article. The above research and experiments demonstrate that SOPC technology provides an efficient, flexible, and low-cost solution for designing embedded Ethernet network terminal devices. The numerous characteristics of SOPC technology make it a competitive solution for embedded systems.