Abstract: This paper describes the DC motor speed control subsystem in an ARM-based embedded intelligent car system. This speed control system mainly consists of an S3C44B0X processor and an L298N motor driver chip. Its main function is to drive the two wheels of the car and adjust its speed and direction. The paper details the relevant register settings and operating modes of the S3C44B0X processor, and provides the system hardware design schematic and software program code. Keywords: S3C44B0X; L298N; Embedded system; DC motor 0 Introduction In the research and development of intelligent cars, a crucial aspect is the ability for the car to autonomously adjust its speed and direction based on surrounding obstacles. The DC motor speed control system designed in this paper is an important component of the intelligent car. It mainly consists of an S3C44B0X processor and an L298N motor driver chip. Its main function is to drive the two wheels of the car, adjust its speed, and regulate its direction by changing the speed difference between the two wheels. 1 Hardware Design The ARM processor, designed by ARM and based on the RISC architecture, boasts high performance, low power consumption, small size, and supports both Thumb (16-bit) and ARM (32-bit) instruction sets, resulting in fast instruction execution. Currently, ARM microprocessors hold over 75% market share in 32-bit RISC embedded products. The ARM7TDMI series is particularly widely used and offers the best price-performance ratio. 1.1 Introduction to S3C44B0X The S3C44B0X is a 16/32-bit RISC processor based on the ARM7TDMI core, launched by Samsung. This processor provides a rich set of general-purpose on-chip peripherals, significantly reducing the number of components other than the processor in the system circuitry. The S3C44B0X has six 16-bit timers, each capable of operating in interrupt or DMA mode. Timers 0, 1, 2, 3, and 4 have PWM functionality, while Timer 5 is an internal timer. Timers 0 and 1, 2 and 3, 4 and 5 each share an 8-bit prescaler, with a prescaler value ranging from 0 to 255. The values ​​of these three prescalers are set via register TCFG0. Timers 0, 1, 2, and 3 also each have a clock divider with five different division signals (1/2, 1/4, 1/8, 1/16, 1/32), while timers 4 and 5 each have a clock divider with four division signals (1/2, 1/4, 1/8, 1/16). The division values ​​for these six timers are set via register TCFG1. The timer input clock frequency = MCLK / Prescaler / Divider. Where MCLK = 60MHz is the system's main frequency. 1.2 Hardware Implementation To improve system efficiency and reduce power consumption, the power amplifier driver circuit uses the L298N integrated circuit based on bipolar H-bridge pulse width modulation (PWM). The L298N is a product of SGS, containing two high-voltage, high-current bridge drivers (H-bridges). It receives standard TTL logic level signals and can drive motors up to 46 volts and 2 amps, with an operating temperature range from -25°C to 130°C. The schematic diagram of one of its internal H-bridges is shown in Figure 1. EnA is the enable pin, controlling the stop of the motor between OUT1 and OUT2. IN1 and IN2, when connected to control levels, control the direction of the motor between OUT1 and OUT2. When the enable pin EnA is active, and IN1 is low and IN2 is high, transistors 2 and 3 are turned on, while 1 and 4 are cut off, causing the motor to reverse. When IN1 and IN2 are at the same level, the motor stops. Table 1 shows the logic relationship between its enable pins, input pins, and output pins. Figure 1. H-bridge schematic diagram. Table 1. Motor operation logic relationship. The other H-bridge operates on the same principle. EnB controls the stop of the motor between OUT3 and OUT4, and the direction of the motor between OUT3 and OUT4 is controlled based on the input levels of IN3 and IN4. Since the S3C44B0X itself has 5 PWM output ports, the control signals can be directly output to the L298N without the need for additional circuitry. The system block diagram is shown in Figure 2. Timers 1 and 2, operating in interrupt mode, are used to generate the PWM signals. I/O ports PE4 and PE5 are programmed as the PWM output ports for Timers 1 and 2, connected to the EnA and EnB ports of the L298N. The speeds of the two DC motors are controlled according to the PWM frequencies output by Timers 1 and 2. PE6 is set as an output port connected to IN1 and then to IN2 via an inverter; similarly, PE7 is also set as an output port, connected to IN3 and then to IN4 via an inverter. By using inverters, IN1 and IN2, and IN3 and IN4, will not be simultaneously at high or low levels, preventing the motors from stopping due to identical levels. Motor stopping can be achieved by setting the pulse width to 0 (duty cycle to 0) or disabling the timer enable bit. This way, only one signal, PE6, is needed to control the states of IN1 and IN2, and PE7 controls the states of IN3 and IN4, thus reducing the number of control signals and simplifying the system to some extent. To ensure the normal operation of the L298N driver chip, four pairs of freewheeling diodes are added between it and the DC motor to shunt the current generated by the back electromotive force in the motor to ground or the positive terminal of the power supply, so as to prevent the back electromotive force from damaging the L298N. Figure 2. System Schematic Diagram 2 System Software Design 2.1 Timer Operation Mode In the S3C44B0X, each timer has a countdown timer, which is driven by the timer clock source to the 16-bit countdown register TCNTn. Before the timer starts, an initial value is written to the timer count buffer register (TCNTBn), and this value is loaded into the countdown timer TCNTn when the timer starts. An initial value is also written to the timer's compare buffer register (TCMPBn), which is used during operation to load into the compare register TCMPn and compare with the value of the countdown timer TCNTn. When the system starts, the values ​​of the TCMPBn and TCNTBn buffers need to be loaded into TCMPn and TCNTn by setting the manual refresh bit. The application of these two buffers (i.e., double buffers) allows the timer to produce a stable output even when the frequency and duty cycle change simultaneously. The general steps to start the timer are as follows: 1) Write the initial value into TCNTBn and TCMPBn. 2) Set the auto-reload bit of the corresponding timer. 3) Set the manual update bit of the corresponding timer, and set the inverter to off. 4) Set the start bit of the corresponding timer to start the timer, and clear the manual update bit. At this time, timer TCNTn starts counting down. When TCNTn has the same value as TCMPn, the logic level of TOUTn changes from low to high. When the counter TCNTn reaches 0, a timer interrupt request will be generated to notify the CPU that the timer operation has been completed. At this time, if the auto-reload control bit is enabled, the value of TCNTBn will be automatically loaded into the TCNTn register, and the next operation cycle will begin. If the timer is stopped by clearing the timer enable bit, the count value will not automatically reload. 2.2 Pulse Width Modulation (PWM) refers to fixing the fundamental period of the output signal and controlling the output power by adjusting the size of the duty cycle within the fundamental period. For a timer, its clock source input frequency generally remains unchanged; that is, the values ​​of TCFG0 (timer prescaler) and TCFG1 (timer divider) do not need to be changed after being set. This provides a stable clock source for PWM. The motor speed is proportional to the voltage across the motor, and the voltage across the motor is directly proportional to the duty cycle of the control waveform. Therefore, the motor speed is proportional to the duty cycle; the larger the duty cycle, the faster the motor rotates. In the system, the PWM pulse frequency is determined by TCNTBn, the PWM pulse width is determined by the value of TCMPBn, and the duty cycle is TCMPn/TCNTn. To decrease the motor speed (i.e., obtain a lower PWM pulse width output value), the value of TCMPBn can be decreased; to increase the motor speed (i.e., obtain a higher PWM output value), the value of TCMPBn can be increased. Due to the characteristics of the double buffer, the TCMPBn value for the next PWM cycle can be written at any point during the low level of the current PWM cycle via an ISR (Interrupt Service Routine) or other means. In other words, the motor speed can be changed by resetting the TCMPBn value through an interrupt in the program. The values ​​of the buffers TCMPBn and TCNTBn are not necessarily equal to the values ​​of TCMPn and TCNTn in this cycle, but they are always the values ​​of TCMPn and TCNTn in the next cycle. 2.3 Program Code The application program in this paper was cross-compiled in the ADS1.2 development environment and downloaded to Flash for execution. Program code (taking Timer 1 as an example): // Initialize port void Init_PortE() { rPCONE=0x5a00; // Define I/O ports // Functions of PE4, PE5, PE6, PE7 rPUPE=0xf8; // Disable pull-up enable of corresponding bits} // Start motor A, which is controlled by Timer 1 void Start_MotorA() { rTCNTB1=Motor_CONT; // Assign values ​​to two buffers rTCMPB1=Motor_cont; rTCON |= (0x01<<11); // Timer 1 auto-reload rTCON |= (0x01<<9); // Manual refresh set rTCON &= ~ (0x01<<10); // Turn off inverter rTCON |= (0x01<<8); // Start Timer 1 rTCON &= ~ (0x01<<9); // Clear manual refresh bit } // Stop motor A void Stop_Motor1() { rTCON &= ~ (0x01<<8); // Clear timer 1 enable bit } // Change motor duty cycle and direction void SetPWM (int valueA, int drct) { rPDATE=drct; // drct defines whether PE6 outputs a high or low level to control the motor direction rTCMPB1=Motor_COUNT*valueA/0x64; //valueA is the duty cycle, or valueA can be set to 0 to stop motor A. } The settings for the other motor are the same as above. During the car's movement, the duty cycles of two sets of PWM can be changed simultaneously to adjust the car's speed; by setting two different duty cycles, the speed difference between the two wheels is formed to change the direction of travel. Comparing the motor drive results with PWM outputs at 100Hz, 1kHz, and 10kHz, it was found that: at 100Hz, the motor operates in an intermittent rotation state; at 10kHz, the motor runs unevenly; and at 1kHz, the motor runs smoothly at different duty cycles, with rapid changes in speed and direction. Figure 3 shows the modulation waveform of the motor in reverse rotation with a PWM frequency of 1kHz and a duty cycle of 30% generated by an oscilloscope. Figure 4 shows the modulation waveform of the motor in forward rotation with a PWM frequency of 1kHz and a duty cycle of 80% generated by an oscilloscope. [align=center] Figure 4 shows the motor in reverse rotation with a duty cycle of 30%[/align] 3 Conclusion The PWM output frequency used in this paper is 1kHz, and the DC motor used is 120 rpm with a rated voltage of 12V (no other inductive load is applied to the motor). This project ultimately realizes an ARM-based embedded intelligent car system, and the PWM speed control of the DC motor is an important subsystem within it. Experiments have shown that Samsung's 16/32-bit RISC processor S3C44B0X is convenient and programmable for PWM modulation, and the motor speed and direction change rapidly and without interruption, which can serve the intelligent car well. References: [1] Du Chunlei ARM Architecture and Programming [M] Beijing: Tsinghua University Press 2003 [2] S3C44B0X USER MANUAL. SAMSUNG ELECTRONICS [3] Tian Ze Embedded Systems and Applications [M] Beijing: Beijing University of Aeronautics and Astronautics Press 2005 [4] Li Hongke Wu Hansong et al. A New Method for Simulation of Brushless DC Motor Control System Based on RTW Microcomputer Information 2005, 06 (006), P12-14