Abstract: This paper describes the hardware platform composition of a wireless sensor network node, detailing the RF chip responsible for wireless transceiver functionality, the sensor module responsible for data acquisition, and the microprocessor responsible for overall operation. The hardware interface design with the CC2420 and EM78815 microprocessors is also presented. Then, the overall software architecture and design of this wireless sensor network system are introduced, mainly including the overall software architecture, hardware driver layer design, and operating system layer design. Keywords: Wireless sensor network; RF chip; Microprocessor; Driver 1 Introduction A wireless sensor network is a multi-hop, self-organizing network system composed of a large number of inexpensive miniature sensors deployed within a monitoring area, formed through wireless communication. Its purpose is to collaboratively sense, collect, and process information about sensed objects within the network coverage area and transmit it to the observer. With the rapid development of microelectromechanical systems (MEMS), self-organizing wireless network technology, and low-power communication technology, research on wireless miniature sensor networks will enter a completely new field. This paper completes the overall design and implementation of a microprocessor-based wireless sensor node. 2 Hardware Architecture Design A wireless sensor network node is a miniature embedded system, generally composed of a sensor module, a processor module, a wireless communication module, and a power supply module, as shown in Figure 1. The arrows in Figure 1 represent the data flow. The sensor module is responsible for collecting and converting information within the monitoring area; the processor module is responsible for controlling the operation of the entire sensor node, storing and processing the data it collects, and data sent from other nodes; the wireless communication module is responsible for wireless communication with other nodes, exchanging control information and sending and receiving collected data; the power supply module provides the energy required for the sensor node to operate, typically using a miniature battery. 3.1 RF Chip CC2420 and Microprocessor EM78815 The CC2420 is a low-cost, low-power, single-chip, highly integrated solution based on the IEEE 802.15.4 standard. It operates on the ISM free band at a frequency of 2.4 GHz. The EM78815, manufactured by ELAN, is a low-power, high-speed 8-bit microcontroller with a RISC architecture. Its main frequency is 3.5862MHz, with 64K program ROM, supporting a maximum of 128K program ROM; 256K×8 on-chip data ROM, supporting a maximum of 2MKB; 4K×8 data RAM; 128 8-bit general purpose registers; and 56 bidirectional, tri-state I/O ports. In addition, it has two 8-bit and one 16-bit hardware timer/counters; a programmable watchdog timer and an on-chip oscillator; and UART and SPI interfaces. The EM78815 has three operating modes: active mode, idle mode, and sleep mode. The mode switching is shown in Figure 2. 3.2 Hardware Interface In this system, the connection between the CC2420 and the EM78815 is shown in Figure 2. [align=center] Figure 2 Interface between CC2420 and EM78815 microprocessor[/align] The CC2420 is connected to the SPI interface via a simple four-wire connection (SI, SO, SCLK, CSn), and the CC2420 is controlled. The EM78815's SPI operates in master mode, acting as the controller for SPI data transmission, while the CC2420 operates as a slave. The CC2420 can be configured to different transmit and receive modes via the modem control register. The CC2420 typically operates in buffered mode (mode 0). In buffered transmit mode (TX_MODE 0), a 128-byte TXFIFO buffer stores the data to be transmitted; in receive mode (RX_MODE 0), a 128-byte RXFIFO buffer stores the received data. The TXFIFO and RXFIFO buffers can be accessed through the TXFIFO (0x3E) and RXFIFO (0x3F) registers. The TXFIFO register is write-only. When data is written to the TXFIFO register, a status word for each new data byte is output on the SO pin. This status byte contains an underflow flag to detect whether an underflow has occurred in the TXFIFO buffer. During each TXFIFO write cycle, 24 bits of data are sent to SI. The first bit of each data frame is set to 0 for register access, the second bit is set to 0 during writing and 1 during reading, followed by 6 address bits (A5:0), and then 16 data bits (D15:0). Similarly, when reading from the RXFIFO register, the address bits are transmitted on SI, and the status and data bits are transmitted on SO. The CSn pin must be kept low during data transfer. Access to the FIFO buffer ends only when CSn goes high. When no bytes are written to the TXFIFO buffer, the TXFIFO buffer emits an underflow pulse, and transmission automatically stops. 3.3 Sensor Module The data acquisition part of the wireless sensor network node can use different sensors depending on the application, such as temperature, humidity, light, pressure, smoke, etc. This system temporarily uses the MAX152 temperature sensor. The MAX152 A/D converter is a high-speed, microcontroller-compatible, 8-bit analog-to-digital converter. Because the chip uses half-flicker conversion technology, low power supply voltage, and tri-state output, it has advantages such as fast conversion, low power consumption, and easy interface with various microcontrollers. The conversion time is only 1.8µs, and the conversion rate is 400×10³ times/s. 3.4 Power Module During the initial system setup, experiments were based on simulation boards and FPGA boards. The simulation boards were powered by ordinary power supplies, while the FPGA boards were powered by AA batteries. In future finished nodes, button batteries will be used. 4 Software Architecture Design As shown in Figure 3, the software of the wireless sensor network node consists of a hardware driver layer, an operating system kernel layer, and an application layer. The hardware driver layer provides drivers for all hardware devices, mainly including the CC2420 driver, ADC module driver, and serial port driver; the operating system kernel layer provides simple and efficient task scheduling, memory management, device management, and wireless communication protocol stack. The application layer mainly involves different users developing corresponding applications using the APIs provided by the operating system layer. Figure 3: Wireless Sensor Network Node Software Architecture Diagram The hardware driver layer mainly implements the functions of peripheral devices and defines some basic interface functions for use by the upper layers. The driver layer design of this system mainly includes board-level initialization based on the EM78815 chip motherboard, configuration of the RF chip transceiver module, ADC module driver, and serial port driver design for the sink node connected to the gateway. 1. Board-level Initialization: Board-level initialization is completed after system power-on reset. The board-level initialization program has complete hardware characteristics and is generally implemented in assembly language, mainly initializing registers and memory. 2. ADC Module Driver Design: The sensors in the ADC module are mainly responsible for sampling information of interest in the surrounding environment and sending it to the MCU for processing via analog-to-digital conversion. The sampling frequency varies depending on the application, and combined with a timer, the surrounding environment is sampled at intervals. The design is relatively simple: when a sampling command arrives, the ADC module is turned on for sampling. After sampling is complete, an AD interrupt is triggered, the MCU handles the interrupt, and shuts down the ADC module for energy saving until the next sampling command or sampling interval arrives. 3. Serial Port Driver Design: In this system, the serial port is mainly responsible for communication between the gateway node and the sink node connected to the gateway: it is responsible for forwarding data received through the wireless channel to the gateway node and also for forwarding commands sent by the gateway node to lower-level nodes. 5 Operating System Kernel Layer Design The operating system is the soul of the node software in a wireless sensor network. Due to the special nature of wireless sensor networks, their operating system requirements differ significantly from those of traditional operating systems. If the operating system is not designed on the node, but instead the application is designed directly on the hardware, it will first increase the difficulty of applications for wireless sensor networks. Application developers will have to program directly to the hardware, unable to obtain the rich services provided by traditional operating systems; moreover, software reusability will be poor, reducing programmer efficiency and increasing development costs. The operating system kernel layer of this wireless sensor system mainly includes task scheduling, memory management, interrupt management, and wireless communication interfaces. 5.1 Task Scheduling In sensor networks, the hardware resources of a single sensor node are limited. If traditional process scheduling methods are used, firstly, the hardware cannot provide sufficient support; secondly, since concurrent operations on sensor nodes may be frequent and the concurrent execution process is very short, traditional process/thread scheduling is also unsuitable. Therefore, a lightweight threading technology, which is simpler than general threads, and a two-layer scheduling method are considered to effectively utilize the limited resources of sensor nodes. In this mode, lightweight threads (i.e., tasks) are scheduled according to FIFS (First-Come, First-Served), and preemption is not allowed between lightweight threads; while hardware processing threads, i.e., interrupt handling threads, can interrupt user lightweight threads and respond quickly to hardware interrupts. Shared resources require access protection through atomic operations or synchronization primitives. 5.2 Interrupt Management The interrupt sources of this system include CC2420's SFD interrupt, FIFOP interrupt, ADC interrupt, timer interrupt, and UART interrupt; software interrupts are not currently used. The UART interrupt only needs to be handled on the sink node connected to the gateway node. This system adopts a scheme called multi-source interrupt, where one interrupt vector corresponds to multiple interrupt sources. There is only one unique interrupt vector, or one interrupt service subroutine entry address, which simplifies the hardware design by requiring only one interrupt service subroutine, but complicates the software design. After entering the interrupt through the unique interrupt vector, the system checks which interrupt source issued the interrupt before entering the corresponding interrupt handler for processing. This system uses software polling instead of hardware to sort the priorities of different interrupt sources, placing higher-priority interrupt sources before the polling procedure, as shown in Figure 4. The polling order is: timer interrupt, SFD interrupt, FIFOP interrupt, and ADC interrupt. [align=center]Figure 4 Interrupt Polling Flowchart[/align] 5.3 Memory Management In this system, because the application is relatively simple and the number of tasks can be statically determined, static memory allocation is used to reduce the uncertainty caused by memory allocation in time. Before system startup, all tasks obtain the required memory. The available memory of the EM78815 mainly includes 128 bytes of bank and 4k bytes of DATARAM. When interrupts, function calls, and task scheduling need to use memory, the compiler allocates memory from the 128 bytes. When requesting global or local variables, the indir keyword needs to be added before the statement to indicate that space is requested from the 4k DATARAM. 5.4 Wireless Communication Protocol The physical layer protocol of this system is designed based on the IEEE 802.15.4 standard. An IEEE 802.15.4 network refers to a collection of devices within a personal operating space that use the same wireless channel and communicate with each other via the IEEE 802.15.4 standard; it is also known as an LR-WPAN network. LR-WPAN networks are simple, low-cost wireless communication networks that enable wireless connectivity in low-power and low-throughput applications. Compared to WLANs, LR-WPAN networks require significantly less infrastructure. The IEEE 802.15.4 standard defines the physical layer and MAC sublayer protocols for LR-WPAN networks. The innovation of this paper lies in the design and implementation of the entire wireless sensor network system. The system's distinctive feature and significance lies in proposing a communication protocol suitable for wireless sensor network nodes based on the EM78815 and CC2420, and improving its communication protocol and operating system scheduling algorithm to better suit existing hardware platforms, thereby better ensuring the success rate and correctness of inter-node communication. References: [1] Sun Limin, Li Jianzhong, Chen Yu. Wireless Sensors. Beijing: Tsinghua University Press, 2005, 1-3 [2] Yu Haibin, Zeng Peng, et al. Research on Communication Protocols of Distributed Wireless Sensor Networks. Journal of Communications, Vol.25(10), 2004, 102-110 [3] Yu Hongyi, Xiao Xiuming. Wireless Mobile Ad Hoc Networks. Beijing: Posts & Telecom Press, 2005 [4] Jiang Chengyan, Wu Siyuan, Chen Wei. Smart Home System Based on Wireless Sensor Networks [J]. Microcomputer Information, 2007, 5-1: 199-201