Abstract: This paper proposes a method for implementing a TDI/CCD (Time Delay Integrator, Charge Coupled Device) driving circuit based on a CPLD (Complex Programmable Logic Device). Altera's MAX7000AE series CPLD is selected as the hardware design platform. The driving timing is described in hardware using VHDL, and the designed driving timing generator is simulated using Quartus II. Measurement and simulation results demonstrate its feasibility. Keywords: Image sensor; Time Delay Integrator, Charge Coupled Device; Complex Programmable Logic Device; Driving Timing Generator Introduction Charge Coupled Devices (CCDs), as emerging solid-state imaging devices, have advantages such as small size, light weight, high resolution, high sensitivity, and good reliability, and are widely used in image sensing, scene recognition, non-contact measurement, and other fields. Compared with ordinary linear CCDs, a major advantage of TDI/CCDs is their ability to operate under low illumination conditions. Simultaneously, TDI/CCDs can reduce the influence of pixel inhomogeneity and fixed pattern noise through multiple exposures, improving the sensitivity and uniformity of visible light CCDs. TDI/CCDs have a wide range of applications in aerospace and other fields. The key to TDI/CCD applications lies in the generation of drive signals and the processing of output signals. Because the drive circuits of different manufacturers and models of TDI/CCD devices vary, the generation of drive signals must be designed according to the specific timing requirements of the TDI/CCD device. Therefore, how to quickly and easily generate TDI/CCD drive timings has become crucial for TDI/CCD applications. Using dedicated ICs to drive TDI/CCDs offers high integration but is expensive, lacking flexibility and portability. Traditional timing generator implementation methods, such as microcontroller-driven, EPROM-driven, and direct digital drive methods, are no longer sufficient to meet the needs of TDI/CCD applications that are moving towards high speed, miniaturization, and intelligence due to speed and functional limitations. Programmable logic devices (CPLDs), with their high integration, high speed, high reliability, and short development cycle, can meet these needs. Their integration with VHDL language can effectively solve the aforementioned problems. Since CPLDs allow for the reconfiguration of their hardware structure and operation through software programming, hardware design can be as convenient and quick as software design. This paper analyzes the working process and timing requirements of Fairchild's CCD525 time-delay integral linear array charge-coupled device chip, and designs a reasonable timing control scheme based on this. A complex programmable logic device (CPLD) is selected as the hardware design platform, and the driving circuit scheme is described in hardware using VHDL. The designed timing generator is successfully simulated using Quartus II. 1. Principle of Optional Output CCD Driving Timing Generator 1.1 Chip Structure Description The Fairchild CCD525 is a four-tap linear array TDI/CCD with an effective pixel count of 2048×96. Its sensor unit size is 13μm (horizontal) × 13μm (vertical), and the number of TDI levels is adjustable to 24, 32, 48, 64, and 96. Each tap has an output frequency of 25MHz, and the total output frequency is 100MHz. The principle structure is shown in Figure 1: [align=center] Figure 1 CCD525 Principle Structure Diagram[/align] Its effective pixel units are transferred in four columns and output from three ports: Vout1, Vout2, Vout3, and Vout4 respectively; the driving pulse consists of vertical transfer clocks V1, V2, V3 and horizontal transfer clocks H1, H2, H3, H4, reset pulse (fw), sampling pulse (cy), synchronization pulse (tb), clamping pulse (qw), background stripping gate pulse (PIG), and integration signal transmitted to the multiplexer control electrode pulse (PTG). Among them, the clamping pulse clamps the output signal to the zero signal level. These signals are all generated by the CCD driving timing generator. 1.2 Driving Timing Analysis One working cycle of TDI/CCD is divided into two stages: optical integration stage and charge transfer stage. During the optical integration stage, the storage gate and the analog shift register are isolated and do not undergo charge transfer. Instead, they operate independently. The storage gate performs optical integration, and the acquired optical signal is transferred to the four output terminals under the action of four-phase horizontal drive pulses. The signals are output in parallel from Vout1, Vout2, Vout3, and Vout4, respectively. The reset signal clears the residual charge in the shift register. During the charge transfer stage, the storage gate and the analog shift register are connected. Under the drive of three-phase vertical transfer pulses, the photogenerated charge obtained from the optical integration of the photosensitive array is transferred in parallel to the charge potential wells of the analog shift register. At this time, the output pulses stop working, and there is no valid signal output from the output terminal. The following are the required timings provided in the CCD525 chip technical datasheet, as shown in Figures 2 and 3: Figure 3 Required horizontal transfer clock timings for the drive circuit. During charge transfer, the three-phase control timings change sequentially. Throughout the cycle, the CDS (Correlated Double Sampling) control signals fw, qw, and cy are always active with a small duty cycle. Due to the randomness of pixel signal noise, a pixel signal column merging method is adopted to improve the system signal-to-noise ratio. That is, every two pixels' signals are shifted out (controlled by horizontal transfer pulse signals), a reset, clamp, and sampling are performed. The first pixel is reset and clamped, and the second pixel is sampled. In this way, the signal charges of adjacent two pixels are integrated and superimposed on the signal storage capacitor of CDS (Correlated Double Sampling) to achieve merging. 2 CPLD Implementation of CCD Driving Timing 2.1 Complex Programmable Logic Device (CPLD) Complex programmable logic devices (CPLDs) include three structures: programmable logic macrocells, programmable I/O units, and programmable internal interconnects. They have certain advantages in speed and have become the preferred devices for high-frequency applications. Considering the high operating frequency of the system, the Altera MAX 7000 series device is selected here. The MAX 7000 series is the industry's fastest series of highly integrated programmable logic devices. It can emulate TTL and can integrate the logic functions of SSI (Small Scale Integration), MSI (Medium Scale Integration), and LSI (Large Scale Integration) at high density. 2.2 VHDL Description of CCD Drive Timing The complex drive timing relationships make the design of drive timing generators large in scale and highly complex, difficult to describe using traditional logic diagrams and Boolean equations. A more abstract description method must be used to achieve top-down design. Hardware Description Language (VHDL) can realize the design of high-level complex logic, realizing the software-based hardware design. The key to designing a TDI/CCD drive timing generator is to describe its drive timing relationships using VHDL and eliminate glitches generated by the CPLD output signal. In this design, Altera's complex programmable logic device MAX7000AE was selected. The TDI/CCD drive timing generator was designed using VHDL programming on the EDA software development platform Quartus II.v5. First, define the input and output terminals of the timing driver: one input terminal: clock input (clk); twelve output signals: vertical transfer clocks V1, V2, V3 and horizontal transfer clocks H1, H2, H3, H4, reset pulse (fw), sampling pulse (cy), synchronization pulse (tb), clamping pulse (qw), background stripping gate pulse (PIG), and control electrode pulse (PTG) for the integration signal transmitted to the multiplexer. The driving of a CCD image sensor is essentially a multi-nested loop. The photosensitive stage and the transfer stage constitute the outer loop of the timing loop, with one loop representing the entire process of one frame of image from exposure to transfer; the row-by-row transfer of the photosensitive stage storage area constitutes the middle loop of the timing loop, with the end of one loop indicating the end of the CCD photosensitive stage; after the row transfer signal ends, the elements of one row of the image are output column by column, forming the inner loop of the timing loop. One cycle represents the transfer of one row of pixels in one frame of image. Counters are used to control the transitions between loops. The overall loop process constitutes the main workflow of the system. Part of the source program is attached below: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity TDI is port (clk1 :in std_logic; h1,h2,h3 :out std_logic; v1 :out std_logic; v2 :out std_logic; v3 :out std_logic; fw :out std_logic; qw :out std_logic; cy :out std_logic; tb :out std_logic; pig,ptg :out std_logic; end TDI; architecture rtl of TDI is component dff - device instantiation... begin process (clk1) begin if (clk1'event and clk1='1') then if (count6="01") then count6<=（others=>'0'）; else count6<=count6 ​​+ 1; end if; end if; —— clk2<=count6（0）; end process; dffx: dff port map(count6（0）,clk1,clk2）; process(clk2) begin if( clk2'event and clk2='1')then if(count1="10")then count1<=（others=>'0'）; else count1<=count1 + 1; end if; end if; end process; ...... 2.3 System simulation of CCD driving timing uses Quartus II The software simulates the driving timing generator. During the entire frame cycle, the system first enters the photosensitive stage, where the pixels in the photosensitive area accumulate charge, while the storage area, transfer register, and output circuit read out the charge signal from the previous frame. Then, in the transfer stage, the pixel charge in the photosensitive area is transferred to the storage area for the entire frame. The system then enters the photosensitive stage again, reading out the signal of the current frame, while the photosensitive area enters the charge accumulation stage for the next frame. An external RC charging circuit is connected to the input reset signal (Op). Upon power-up, the input is low, resetting all system signals; after a short delay, it becomes high, and the system starts running. The Quartus II software selects the appropriate CPLD device based on the system design, choosing Altera's EPM7128SLC84-7. The driving timing simulation waveforms are shown in Figures 4 and 5 (comparing the vertical and horizontal transfer clock specifications given in Fairchild's technical data). 3. Conclusion The above design is the first to use a CPLD instead of a traditional IC to achieve timing drive for TDI/CCD. The simulation results meet Fairchild's requirements. The company's technical data provides a vertical transfer clock enable time of 750ns and a horizontal transfer clock cycle of 40ns. In the test conducted by the Chongqing Institute of Optoelectronics, the driving timing generator can effectively drive the TDI/CCD chip and CDS (correlated double sampling) signal, and its operation is stable and reliable. Its development and manufacturing process simplifies the previous hardware development and manufacturing process. References 1 Wang Qingyou. Image sensor application technology. Tianjin: Electronic Industry Press, 2003 2 Song Wanjie, Luo Feng, Wu Shunjun. CPLD technology and its application. Xi'an: Xi'an University of Electronic Science and Technology Press, 2000 3 Gu Lin, Hu Xiaodong, Luo Changzhou, et al. Adaptive adjustment of optical integration time of linear TDI/CCD based on CPLD. Acta Photonica Sinica, 2002, 31 (12): 1533-1537 4 Zhang Hu, Li Zitian, Wen Desheng. A timing generation method for multi-TDI/CCD system. Microcomputer Applications, 2002 ,23 (5):296～298