Abstract: Taking an ARM-based embedded minimum system as a platform, this paper delves into the interface methods between ARM processors and commonly used external memories under different applications. Based on this, it elucidates the typical boot architecture and characteristics of embedded systems and provides selection criteria for embedded system boot architectures. Keywords: Embedded minimum system; ARM; Interface method; Boot architecture 1. Introduction With the rapid development of embedded technologies, embedded systems are becoming increasingly powerful and their application interfaces are becoming richer. Designing specific embedded minimum systems and application systems according to the needs of actual applications is crucial for embedded system design. Currently, in the process of embedded system development, developers often devote a lot of energy to the connection methods between the embedded microprocessor (MPU) and numerous peripherals, as well as the development of application code, while neglecting the research on the most basic and core parts of the embedded system. Currently, in the embedded field, ARM (Advanced RISC Machines) processors are widely used in various embedded devices. Because ARM embedded architectures are similar and have common peripheral circuits, and the design principles and methods of ARM core embedded minimum systems are basically the same, the research on embedded minimum systems is of vital importance in the entire system development process. This paper uses an ARM-based embedded minimum system as a platform and studies its architecture from both hardware and software perspectives. The hardware aspect mainly introduces the interface technology between the ARM processor and typical external memory, while the software aspect focuses on a detailed analysis of the embedded minimum system's boot architecture. 2. Embedded Minimum System An embedded minimum system is a minimal module configuration that enables system operation while minimizing the number of upper-layer applications. For a typical embedded minimum system, taking an ARM processor as an example, its constituent modules and their functions are shown in Figure 1. The ARM microprocessor, FLASH, and SDRAM modules are the core components of the embedded minimum system. [align=center] Figure 1 Minimum System Structure[/align] ● Clock Module - Usually multiplied by the ARM internal phase-locked loop to provide the clock frequency input required for the operation of each module of the system ● Flash Storage Module - Stores the boot code, operating system and user application code ● SDRAM Module - Provides dynamic storage space for system operation and is the main area for system code execution ● JTAG Module - Enables downloading and debugging of program code ● UART Module - Enables terminal display of debugging information ● Reset Module - Enables system reset 3. External Memory Interface Technology The interface technology between the ARM processor and external memory (Flash and SDRAM) is the key to the hardware design of the embedded minimum system. Choosing a reasonable interface method according to the needs can effectively improve the overall performance of the embedded system. 3.1 Introduction to Commonly Used External Memory (1) Nor Flash and Nand Flash Nor Flash, also known as linear Flash, has high reliability and fast random read speed. It has the characteristics of execution in place (XIP), so the application program can run directly in the Flash memory without having to read the code into the system RAM. It is commonly used in situations where there are few erase and programming operations and the code is executed directly. Nand Flash is an ideal solution for high data storage density. It is generally used for data storage and file storage. It is erased in blocks and has the advantage of fast erasure speed. (2) Synchronous Dynamic Random Access Memory (SDRAM) SDRAM (Synchronous Dynamic Random Access Memory) is an improvement on the early DRAM. It is synchronous memory and introduces the CLK signal in the interface signal. All data, address and control signals are aligned with the rising edge of CLK. In addition, SDRAM also introduces a command controller inside. The processor accesses SDRAM by sending commands to the command controller. 3.2 ARM processor and Flash interface technology 3.2.1 ARM processor and Nor Flash interface technology Nor Flash has an SRAM interface and enough address pins, which can easily address the memory cells inside the memory. In the actual system, the connection method between the ARM processor and Nor Flash can be selected as needed. Figure 2 shows two different connection methods between the ARM processor and Nor Flash in the case of an embedded minimum system containing two Nor Flash. [align=center] Figure 2 Nor Flash Interface Methods[/align] (1) Dual Flash Independent Chip Select This method treats two Nor Flash chips as independent units for processing. Depending on the application requirements, the boot code can be stored in one Flash and the file system can be established in the other Flash to store the application code. This method is convenient to operate and easy to manage. (2) Dual Flash Unified Chip Select This method treats two Nor Flash chips as one unit for processing. The ARM processor accesses them as a parallel processing unit. In this example, two 8-bit Nor Flash chips SST39VF1601 are used as a 16-bit unit for processing. This can be used as a reference for the connection method of N (N>2) Flash blocks. 3.2.2 ARM Processor and Nand Flash Interface Technology The Nand Flash interface has relatively few signals, and the address, data and command buses are multiplexed. The Nand Flash interface is essentially an I/O interface. When the system accesses data from the Nand Flash, it needs to send relevant commands and parameters to the Nand Flash first, and then perform the corresponding data operations. There are three main ways to connect an ARM processor to a Nand Flash, as shown in Figure 3: [align=center] Figure 3 Nand Flash Interface Methods[/align] (1) Using GPIO Method Using GPIO pins to control various signals of the Nand Flash can fully utilize the performance of the NAND device when the speed requirement is relatively low. It will greatly facilitate meeting the time domain requirements of the NAND device, making it easy for the ARM processor to control the NAND device. This method requires the processor to provide sufficient GPIO. (2) Using Logical Operation Method In this method, the processor's read and write enable signals drive the corresponding read and write signals of the NAND device after performing logical operations with the chip select signal CS. Example b in Figure 3 shows the connection method between the Samsung ARM7TDMI series processor S3C44B0 and the Nand Flash K9F2808U0C. (3) Direct Chip Enable Some ARM processors, such as the S3C2410, provide corresponding control registers for the NAND device. Through the control registers, the ARM processor can drive the corresponding signals of the NAND device. This method simplifies and standardizes the connection between the ARM processor and the NAND device. Example c in Figure 3 shows the connection between the ARM processor S3C2410 and the NAND Flash K9F2808U0C. 3.3 ARM Processor and SDRAM Interface Technology The external dynamic memory module of the embedded minimum system generally uses SDRAM. Most ARM processors now have an integrated SDRAM controller, which can easily access every byte inside the SDRAM. In actual development, one or more SDRAM chips can be selected as needed. Figure 4 shows two commonly used interface methods. [align=center] Figure 4 SDRAM Interface Methods[/align] (1) Single SDRAM Example a in Figure 4 shows the connection between the ARM processor S3C44B0 and a 16-bit SDRAM K4S641632d. This connection method is often used in embedded systems with strict size limitations and low requirements for dynamic memory capacity. (2) Dual 16-bit SDRAMs Combined: When two 16-bit SDRAMs are combined to form a 32-bit SDRAM, the ARM processor's address line A2 is connected to the SDRAM's address line A0, and the remaining addresses are sequentially incremented. This is because a byte is the only unit of storage capacity in SDRAM, and the SDRAM is 32-bit wide at this time. The BA address lines of the SDRAM are the address lines of its internal Bank, representing the highest bit of the SDRAM memory. In example b of Figure 4, the total size of the SDRAM is 64M (64M = ), which requires pins A25-A0 for addressing, so BA1-BA0 are connected to pins A25-A24. It should also be noted that the row address and column address of SDRAM memory are multiplexed, so the number of address lines is generally less than 26. For specific connections, refer to the relevant manuals of the ARM processor and SDRAM. It is worth noting that some ARM processors, such as Samsung's ARM940T series processor S3C2510, have an address bus that is different from other standard ARM processors. Its address lines are divided into internal address lines and external address lines. Based on the width of the connected memory data bus, the internal address lines are shifted accordingly to correspond to the external address lines A23-A0, thus providing fixed address lines A23-A0 externally. Its essence is consistent with typical ARM processors. 4. Embedded System Boot Architecture The boot architecture is a key technology in embedded systems. Mastering the boot architecture is crucial for understanding the operating principles of embedded systems. During the boot process of an embedded system, the execution of the boot code, the operation of the operating system, and the loading of applications mainly follow two architectures: one is a direct boot architecture from Nor Flash, and the other is a direct boot architecture from Nand Flash. It is important to note that various situations can occur during the embedded system boot process. For example, VxWorks' boot code BootRom has compressed and uncompressed, resident and non-resident modes, and the operating system itself is often stored in compressed image mode. Therefore, the boot code needs to be processed accordingly during execution and loading. 4.1 Booting from Nor Flash Nor Flash has the characteristic of execution-in-place (XIP), and is often the first choice for storing boot code in embedded systems. The architecture for booting from Nor Flash can be further subdivided into boot architectures that use only Nor Flash and boot architectures that use Nor Flash in combination with Nand Flash. Figure 5 shows the block diagrams of these two boot architectures. [align=center] Figure 5 Boot Architecture [/align] 4.1.1 Using Nor Flash Alone In this architecture, the boot code, operating system, and application code coexist in the same Nor Flash. After the system powers on, the boot code executes first in the Nor Flash, and then the operating system and application code are loaded into the faster SDRAM to run. Another feasible architecture is to execute the boot code and operating system in the Nor Flash, while only loading the application code into the SDRAM for execution. This architecture makes full use of the characteristics of execution within the Nor Flash chip, which can effectively improve system performance. The disadvantage is that as the capacity of the operating system and application code increases, a larger capacity and more expensive Nor Flash is required to support it. 4.1.2 Using Nor Flash and Nand Flash in Combination The use of Nor Flash alone will increase the cost of products for applications with large amounts of code. One improvement is to adopt an architecture that uses Nor Flash and Nand Flash in combination. This architecture includes an additional Nand Flash memory. The Nor Flash (2MB or 4MB) stores the boot code and operating system (the operating system can be stored in either Nor Flash or Nand Flash depending on its size), while the Nand Flash stores the application code. The Nand Flash capacity can be adjusted based on the size of the application code. After power-on, the boot code executes directly in the Nor Flash, while the operating system and application code from the Nand Flash are loaded into the faster SDRAM for execution. Alternatively, the boot code and operating system can be executed in the Nor Flash, while only the application code from the Nand Flash is loaded into the SDRAM for execution. This architecture is one of the most widely used boot architectures in current embedded systems. 4.1.2 Booting from Nand Flash Some processors, such as Samsung's ARM920T series processor S3C2410, support booting from Nand Flash. Its working principle is to load the first 4KB of code stored in the Nand Flash into an address called Steppingstone (BootSRAM), and then begin executing this boot code, thereby completing the loading of the operating system and application programs. This method requires the processor to have an internal NAND controller and also requires a certain amount of additional SRAM space, which has certain limitations and is rarely used in actual development. 5. Conclusion The author's innovation is based on the commonality of the ARM architecture. Taking the ARM-based embedded minimum system as the platform, the architecture of the system is studied from both hardware and software aspects. The hardware aspect describes the interface between the ARM processor and commonly used external memory. The software aspect gives the typical startup architecture of the embedded minimum system and its selection criteria. References: [1] Li Bie. ARM development platform based on S3C4510B[J]. Microcomputer Information, 2006, 10-2: 34-36. [2] Zhang Lun. Hardware design and debugging of 32-bit embedded system[M]. Beijing: Machinery Industry Press, 2005. 60-61. [3] NAND Flash Applications Design Guide[EB/OL]. http://www.toshiba.com. About the author: Wang Genyi (1956-), male, from Liquan, Shaanxi, senior lecturer, mainly engaged in computer science and electronic technology research. Ma Debao (1982-), male, from Yuzhou, Henan Province, holds a master's degree and his research interests are embedded systems and their networked applications. Yang Libin (1981-), male, from Ji'an, Jiangxi Province, holds a doctoral degree and his research interests are embedded systems and wireless network applications.