Abstract : Since the common-mode voltage output of a two-level inverter can only be eliminated by an external filter, this paper studies the common-mode voltage suppression technology of a three-level PWM inverter. Using the effective switching states of the three-level inverter, the causes of common-mode voltage generation in the three-level inverter are analyzed, concluding that the common-mode voltage of an odd-level inverter can be suppressed by software methods. For the commonly used inverter control strategy—PWM—an improved strategy for reducing and eliminating common-mode voltage is proposed, and its correctness is verified by simulation results. The paper also compares the impact of different modulation strategies on motor performance, verifying the applicability of the proposed strategy. Keywords : Power engineering; Common-mode voltage; Sinusoidal pulse width modulation; Three-level inverter; Sinusoidal pulse width modulation 1 Introduction The common-mode voltage generated in the motor windings by a traditional two-level PWM inverter can lead to negative effects on the motor and drive system. Specifically, the common-mode voltage establishes a shaft voltage between the rotor and the housing through electrostatic coupling. When the shaft voltage exceeds the insulation capacity of the bearing lubricant, excessive bearing current will be generated. Bearing current can cause premature damage to the motor bearings. Meanwhile, common-mode voltage generates very large common-mode leakage current, which flows to ground through electrostatic coupling between the stator winding and the grounded chassis. This can generate sufficiently large common-mode electromagnetic interference and cause leakage current protection relays to malfunction. Existing elimination techniques are generally used to suppress bearing current and conducted electromagnetic interference, but few can be directly and successfully applied to common-mode voltage suppression. The filters proposed in the literature can be directly used to suppress common-mode voltage with very significant suppression effects, but require the common-mode transformer to be large enough. There is even less literature on multi-level PWM technology for suppressing common-mode voltage. In addition to hardware methods, from a control strategy perspective, the literature introduces a space vector algorithm, which can reduce the voltage between the neutral point of the motor stator winding and ground to 2Vdc/3 by synchronizing the switching sequences of the rectifier and the inverter. However, this method requires controllable rectifier inverters and is not suitable for diode inverters, which have a wider range of applications. This paper will discuss common-mode voltage suppression methods in multi-level inverters and use Matlab simulation software to verify the effectiveness of the methods. The common structure of multilevel PWM inverters is the diode-clamped multilevel inverter (NPC), which spans capacitor-type multilevel inverters and cascaded inverters. They are commonly used in medium-voltage (2300/4160V) devices to reduce the rated voltage of power switching devices, thereby reducing harmonic components in the output voltage. This article uses the diode-clamped multilevel inverter as an example to analyze common-mode voltage suppression technology; the conclusions can be extended to other structures. [b][align=center]For more details, please click: Research on Common-Mode Voltage Suppression Technology in Multilevel SPWM Inverters[/align][/b]