Introduction CAN (Controller Area Network) is an industrial fieldbus, a communication protocol developed by Bosch in the early 1980s to solve the data exchange problem between numerous control and testing instruments in modern automobiles. In November 1993, ISO officially issued the international standard for high-speed communication control area networks (CAN) (ISO 11898). In CAN bus systems, field data acquisition is accomplished by sensors. Currently, there are not many types of sensors with CAN bus interfaces, and they are relatively expensive. This paper presents an intelligent node circuit based on an 8051 microcontroller and an 82527 independent CAN bus controller, forming an intelligent sensor node capable of receiving 8 analog inputs based on ordinary sensors. 1 Introduction to the Independent CAN Bus Controller 82527 The 82527 is an independent CAN bus controller manufactured by Intel. It can interface with Intel and Motorola controllers via a parallel bus; it supports the CAN protocol 2.0B standard, has receiving and transmitting functions, and can perform message filtering. The 82527 is manufactured using CHMOS 5V process, in a 44-pin PLCC package, and has an operating temperature of -44 to +125℃. The pin arrangement and definition are described in reference [1]. (1) Clock signal of 82527 The operation of 82527 is controlled by two clocks: system clock SCLK and register clock MCLK. SCLK is obtained from an external crystal oscillator, and MCLK is obtained by dividing SCLK. The bit timing of the CAN bus is based on the frequency of SCLK, while MCLK provides the clock for register operations. The frequency of SCLK can be equal to the external crystal oscillator XTAL, or it can be 1/2 of its frequency; the frequency of MCLK can be equal to SCLK or 1/2 of its frequency. The default settings after system reset are SCLK=XTAL/2, MCLK=SCLK/2. (2) Working modes of 82527 82527 has 5 working modes: Intel mode 8-bit time-sharing mode; Intel mode 16-bit time-sharing mode; serial interface mode; non-Intel mode 8-bit time-sharing mode; 8-bit non-time-sharing mode. This paper uses the Intel mode 8-bit time-sharing mode, in which case pins 30 and 44 of 82527 are grounded. (3) Register structure of 82527 [2] The register addresses of 82527 are 00～FFH. The registers are introduced below as needed. ① Control register (00H): CCE——Change configuration enable bit, active high level. When this bit is active, the CPU is allowed to write to configuration registers 1FH, 2FH, 3FH, 4FH, 9FH, AFH. EIE——Error interrupt enable bit, active high level. This bit is usually set to 1, and the CPU is interrupted when an abnormal number of errors occur on the bus. SIE——State change interrupt enable bit, active high level. This bit is usually set to 0. IE——Interrupt enable bit, active high level. INIT—Software initialization enable bit, active high. When this bit is active, CAN stops sending and receiving messages, and TX0 and TX1 are recessive level 1. This bit is set during hardware reset and bus shutdown. ②CPU Interface Register (02H): RSTST—Hardware reset status bit. This bit is written by the 82527; when it is 1, hardware reset is activated, disallowing access to the 82527; when it is 0, access to the 82527 is allowed. DSC—SCLK divider bit. When this bit is 1, SCLK = XTAL/2; when it is 0, SCLK = XTAL. DMC—MCLK divider bit. When this bit is 1, MCLK = SCLK/2; when it is 0, MCLK = SCLK. PWD—Power-down mode enable bit, active high. SLEEP—Sleep mode enable bit, active high. MUX—Low-speed physical layer multiplexing flag bit. When this bit is 1, ISO low-speed physical layer is activated, PIN24=VCC/2, PIN11=INT# (# indicates inversion); when this bit is 0, PIN24=INT#, PIN11=P2.6. CEN—Clock output enable bit, active high. ③Standard global mask register (06～07H). This register is used for messages with standard identifiers, or message registers with XTD set to 0. This method is called message receive filtering. When a bit is 1, the corresponding bit of the message identifier must match; when it is 0, it does not need to match. ④Extended global mask register (08～0BH). This register is used for extended message formats, or message registers with XTD set to 1, and its function is the same as ③. ⑤Bus configuration register (2FH): COBY—Bypass input comparator flag bit, active high. POL—Polarity flag bit. When it is 1, if the bypass input comparator is used, logic 1 at the input of RX0 is dominant, and logic 0 is recessive; when it is 0, the opposite is true. DCT1—TX1 output cut-off control bit. 1 indicates TX1 output is not driven; this mode is used for a single bus with the two differential wires short-circuited. 0 indicates TX1 output is driven. DCR1—RX1 input cut-off control bit. 1 indicates RX1 is disconnected from the inverting input of the input comparator and connected to VCC/2. 0 indicates RX1 is connected to the inverting input of the input comparator. DCR0—RX0 input cut-off control bit. Same function as DCR1, but RX0 is connected to the non-inverting input of the comparator. ⑥ Timer Register 0 (3FH): SJW—Synchronization jump width bit field, programmed value 1-3. BRP—Baud rate divider bit field, programmed value 0-63. ⑦ Timer Register 1 (4FH): SPL—Sampling mode flag bit. 1 indicates 3 samples per bit; 0 indicates 1 sample per bit. TSEG1—Time period 1 bit field, programmed value 2-15. TSEG1—Time period 2 bit field, programmed value 1-7. Baud rate = XTAL / [(DSC+1) * (BRP+1) * (3 + TSEG1 + TSEG2)] ⑧ Message registers (using the first byte address of each register as the base address BASE). ◇ Control registers 0,1 (BASE+0, BASET+1) MSGVAL—Message register valid flag, active high. 10 for set, 01 for reset. TXIE—Transmit interrupt enable flag, active high. 10 for set, 01 for reset. RXIE—Receive interrupt enable flag, active high. 10 for set, 01 for reset. INTPND—Interrupt request flag, active high. 10 for set, 01 for reset. RMTPND—Remote frame request flag, active high. 10 for set, 01 for reset. TXRQST—Request to transmit flag, active high. 10 for set, 01 for reset. MSGLST—Message lost flag, used only for receive message registers. 10 indicates that an unread message has been overwritten by a new message, and 01 indicates that it has not been overwritten. CPUUPD—CPU update flag, used only for sending message registers. 10 indicates the message will not be sent, 01 indicates the message can be sent. NEWDAT—New data flag. 10 indicates that new data has been written to the register, 01 indicates that no new data has been written. ◇ Arbitration registers 0, 1, 2, 3 (BASE+2-BASE+5) store message identifiers. ◇ Message configuration register (BASE+6) DLC—Data length encoding, programmed values ​​0-8. DIR—Direction flag. 1 for sending, 0 for receiving. XTD—Standard/Extended identifier flag. 1 for extended identifier, 0 for standard identifier. ◇ Data registers (BASE+7-BASE+14) When the 82527 stores a message, all 8 data bytes are written; unused bytes are randomized. 2 Hardware Circuit Design The circuit of the intelligent node is shown in Figure 1 (6264 is omitted in the figure). In the hardware design, the ADC0809 performs the conversion of 8 analog signals. Information exchange with the 8051 uses a polling method, with addresses BFF8～BFFFH, and its clock can be obtained by dividing the frequency by ALE. The 82527 handles information exchange with the CAN bus. In this design, the input comparator is bypassed, and information exchange with the 8051 uses an interrupt method, with addresses 7F00～7FFFH. The P1 and P2 ports of the 82527 can be used for digital signal acquisition or relay control. The 82C250 provides the interface between the 82527 and the physical bus, improving receiving and transmitting capabilities. The program memory can be expanded as needed. 3 Software Design The software for this design is written in MCS-51 assembly language, and the program flowchart is shown in Figure 2. The initialization procedure for the 82527 is as follows: INT: MOV DPTR, #0FF02H MOV A, #00H MOVX @DPTR, A ;SCLK=XTAL ;MCLK=SCLK,CLKOUT invalid MOV DPTR, #0FF00H MOV A, #41H MOVX @DPTR, A ;Set CCE, INIT MOV DPTR, #0FF2FH MOV A, #48H MOVX @DPTR, A ;Bypass input comparator sets 1 bit to recessive, 0 to dominant, RX1 invalid MOV DPTR, #0FF3FH; MOV A, #43H; MOVX @DPTR, A ;SJW=2,BRP=3 MOV DPTR, #0FF4FH MOV A, #0EAH MOVX @DPTR, A ;SPL=1,TSEG1=7,TSEG2=6 The baud rate is 100Kbps at this time. MOV DPTR,#0FF00H; MOV A,#01H MOVX @DPTR,A ;Disable access to configuration registers MOV DPTR,#0FF10H; MOV A,#55H; MOVX @DPTR,A; INC DPTR; MOVX @DPTR,A; · · · MOV DPTR,#0FFF0H; MOV A,#55H; MOVX @DPTR,A INC DPTR; MOVX @DPTR,A ;Initialize message register control bits MOV R0,#06H; MOV DPTR,#0FF06H; MOV A,#0FFH; L1: MOVX @DPTR,A ;Message identifiers must all match INC DPTR DJNZ R0,L1; MOV DPTR,#0FF16H; MOV A, #8CH ; Message register 1 can send an 8-byte extended message. MOVX @DPTR, A; MOV DPTR, #0FF26H; MOV A, #84H; MOVX @DPTR, A ; Message register 2 can receive an 8-byte extended message. MOV DPTR, #0FF00H; MOV A, #00H; MOVX @DPTR, A ; Initialization ends. RET