1 Introduction With the increasing demands for real-time signal processing in intelligent instruments and control systems, and the rapid development of large-scale integrated circuit technology, there is an increasingly urgent need for a high-performance design solution. Combining DSP and ARM technologies in embedded systems will fully leverage the advantages of both to meet the real-time and efficient communication requirements of intelligent control systems. This embedded system requires real-time response and strict timing. Its operating environment may be very harsh, such as high temperature, low temperature, and humidity, so the system also requires very high stability. 2 Overall Design of the Embedded System 2.1 Main Functions of Core Devices The ARM and DSP selected are Cirrus Logic's EP7312 and TI's TMS320VC5402, respectively. By fully utilizing the rich on-chip resources of the ARM and the powerful signal processing capabilities of the DSP, efficient and real-time signal processing and network communication functions are achieved. The EP7312 is a microprocessor designed for high-performance, ultra-low-power products. It uses the ARM7TDMI processor core, features an 8kB high-speed cache, supports a memory management unit, and integrates an LCD controller, keyboard scanner, digital audio interface, and full JTAG functionality. It is widely used in embedded systems. The TMS320C54xDSP provides McBSPs (Multi-channel Buffered Serial Ports); a 6-channel DMA controller; and an 8-bit enhanced HPI (Host Interface) for direct communication with external processors. Choosing such a SoC (System-on-a-Chip) as the core device ensures stability, reliability, and extensive expansion capabilities. 2.2 System Overall Design and Working Principle The overall system design block diagram is shown in Figure 1. This system mainly implements real-time signal processing and transmission to meet the high reliability requirements of industrial sites and various measuring instruments. ARM has abundant on-chip resources, suitable for embedded system development. In this embedded system, the ARM is mainly responsible for operating system operation, task management and coordination, and DSP control tasks, completing remote data communication. Various external peripherals are added, such as a general-purpose serial port, LCD display, and Ethernet interface. Networking functionality is achieved by connecting to an Ethernet controller. The Linux operating system and drivers for the system's external hardware interfaces are ported to the ARM processor. The DSP performs computationally intensive operations, implementing various signal processing algorithms, and then communicates the processed digital signals with the ARM processor via the host interface (HPI). The ARM processor then transmits the data to the network via the Ethernet controller, enabling remote control and monitoring. [align=center] Figure 1 Overall System Hardware Block Diagram[/align] 3 System Hardware Specific Design Scheme 3.1 ARM and DSP Interface Design The interface circuit connecting the EP7312 and TMS320VC5402 is shown in Figure 2. The VC5402 connects to the ARM processor via HPI. The ARM processor first writes a control word to the DSP to set the operating mode, then writes the access address to the address register (HPIA), and then reads and writes the data latch (HPID) to read and write the specified memory unit. The host can address all control registers, address registers, and data registers of the HPI interface using two address lines A2 and A1; HBIL, HCNTL1, and HCNTL0 distinguish the high and low bytes of the 16-bit data. When writing data to the address HBIL=0, it indicates the first byte; writing data to the address HBIL=1 indicates the second byte. HCS must be low during addressing. The DSP's HPI interface chip select signal uses the EP7312 extended chip select signal nCS4. The mapped addresses of the HPI special function registers are as follows: After setting the DSP's state, the DSP sends an interrupt to the ARM, notifying the ARM that the data is ready and waiting for the ARM to send an interrupt. The DSP processes the received data in the interrupt. After initialization, the ARM waits for the DSP to send an interrupt notification that the data is ready. After detecting the interrupt, the ARM first checks if the interrupt is valid, then reads and writes data from the HPI port. After completing the data transmission to the HPI port, it sends an interrupt to the DSP to notify the DSP to receive the data. The ARM uses control port signals to simulate interface timing to access the HPI port registers. Because the DSP sends an interrupt to the ARM during the BOOT process, the ARM must clear this interrupt during initialization and set the BOB bit in the control register before data exchange to indicate whether the high address comes first or the low address comes first. This step is performed by the ARM during program initialization. 3.2 Communication Design between ARM and Ethernet Controller The system platform implements an Ethernet interface. A driver for the Ethernet chip is provided to support network functions. The data, address, and control signals of the Ethernet controller chip are connected to the bus of the EP7312, as shown in Figure 3. The chip select signal uses the extended chip select signal nCS2 of the EP7312. [align=center] Figure 3 Ethernet Interface Schematic[/align] The default I/O base address of the RTL8019 is 300H, and the address space used is 300H～3FFH. Therefore, the lower 4 address lines of the EP7312 are used. SA19～SA10 and SA7～SA5 on the RTL8019 are connected to ground, and SA9 and SA8 are connected to VCC. The RTL8019AS uses a 16-bit data bus mode. Therefore, the IOCS16B pin on the RTL8019 is connected to VCC through a 10K pull-up resistor. Since the Ethernet controller is read and written in IO mode, the SMEMRB and SMEMWB pins are connected to VCC through pull-up resistors. When the EP7312 sends data over the network, it first sends a frame of data to the transmit buffer in the RTL8019AS via the remote DMA channel, and then issues a transmission command. The RTL8019AS only begins transmitting the current frame after completing the previous frame's transmission. Data received by the RTL8019AS is compared via MAC and checked via CRC, then stored in the receive buffer via FIFO. Once a frame is full, the RTL8019AS notifies the EP7312 via an interrupt. The FIFO logic buffers transmitted and received data by 16 bytes to reduce the frequency of local DMA requests. The Ethernet controller has two pointer registers to control the buffer's storage process: the current page pointer `curr` and the boundary pointer `bnry`. `curr` points to the starting page of the newly received frame, i.e., the write page pointer of the receive buffer ring; `bnry` points to the last page read, i.e., the read page pointer of the receive buffer ring. A user-defined pointer `next_page` represents the boundary of the storage packet buffer. Its initial value is `next_page = bnry`. After reading a page of data, `bnry` is incremented by 1 by software, and `curr` is automatically incremented by 1. When curr is not equal to bnry, it means that there is a new data packet in the buffer. Read the first four bytes of a packet. The first four bytes are not the content of the Ethernet data packet. They represent the page address where the data packet is stored and the number of bytes of data received, respectively. If curr=0, it means that the reading has failed and null is returned. If bnry>0x7f, then bnry=0x4c. 4 Embedded System Software Design 4.1 BootLoader Design This embedded system introduces the Linux operating system, which can provide a scheduling mechanism for tasks under the system, simplify the required operations in the task. When the requirements change, only the task content needs to be changed and then redeployed with the operating system. In this system, EP7312 adopts the external boot method, that is, it starts from the external NORFLASH selected by CS[0]. After the system starts, the boot code is executed, that is, the CPU, memory controller and on-chip device are initialized, and then the storage mapping is configured. The boot code then executes a bootloader, which decompresses the kernel from FLASH to SRAM, and then jumps to the first instruction of the kernel to execute. The kernel runs. The bootloader completes the transition from hardware boot to operating system boot, and is used to initialize the hardware and start the operating system. Before the kernel runs, a bootloader is needed as a system driver to load the kernel and perform some auxiliary tasks, then jump to the starting address of the kernel code and execute it. For this system, the bootloader used by EP7211—Shoehorn—was selected, and some modifications were made. These included adjusting the address values ​​of various system registers, configuring the SDRAM controller, and adjusting the baud rate of UART1. The Shoehorn code is divided into two parts: the host side and the target side. One part consists of eth.c, serial.c, shoehorn.c, and util.c, which are compiled to generate the executable file shoehorn for the host side. The other part consists of ini.s and loader.c, which are compiled to generate a file less than 2KB, loader.bin. This binary file is downloaded to the SRAM on the target side to boot the system. Through a series of handshakes and communication between the host and the development board, and by downloading the program, the code is relatively dispersed, reducing the size of the initial code on the development board to meet the download code limitations on the target board. 4.2 Kernel Configuration This embedded system selected the relatively mature and stable Linux-2.4.13 kernel. To avoid instability and loss of flexibility caused by modifying custom kernel code, a suitable kernel version can be selected, the configuration file modified, unnecessary functions removed, and a kernel tailored to the new configuration compiled. This results in a kernel that meets application requirements while maintaining a small size, generating a hidden file `/usr/src/linux/.config`. This file records the selection and configuration of specific kernel modules. During kernel configuration, most options can use default values, with only a small portion requiring selection based on needs. Frequently used functions closely related to the kernel are directly compiled into the kernel; less frequently used code is compiled into loadable modules, which helps reduce kernel length and increase flexibility. 4.3 Driver Design In the Linux operating system, a driver is the direct interface between the operating system kernel and hardware devices. Drivers shield the details of the hardware. From the application's perspective, hardware devices are operated as if they were simply files. Device drivers can be designed modularly. They do not need to be compiled into the kernel but are compiled separately and linked into a set of object files. These files can be loaded into or unloaded from the running kernel. This reduces kernel length and provides significant flexibility. 4.4 Implementation of Signal Processing Algorithms in DSP Most sensors exhibit cross-sensitivities to environmental factors such as temperature, humidity, and power supply fluctuations, leading to significant errors and impacting measurement accuracy and stability. Data fusion technology in DSP can eliminate interference and improve sensor measurement accuracy. Data fusion involves combining sensor data and correlating them to obtain more information from the output elements, ensuring high measurement accuracy and stability even under conditions of significant environmental interference. Software-based sensor data fusion processing has proven to be an effective method. The system's network functionality allows for the connection of multiple embedded intelligent instruments with similar or different functions to form an intelligent sensor network. Each intelligent instrument node possesses data acquisition, data processing, and communication capabilities. Information fusion technology can process data from multiple sensors at multiple levels, aspects, and layers, generating new and meaningful information—information about the objective environment with higher accuracy than that obtained by any single sensor. This technology plays a crucial role in sensor networks. 5 Conclusion The design of this embedded intelligent instrument system provides an excellent solution for convenient and effective Ethernet access for instruments, enabling remote control and real-time data transmission. By employing concurrent multitasking technology to handle complex external events and the complexity of the control software system, the real-time performance of this embedded system is guaranteed. The embedded system features streamlined hardware and software configurations, meets environmental requirements for interference resistance, and its assembly structure facilitates maintenance. The implementation of this embedded intelligent instrument system enables the successful application of embedded design in the fields of data processing and detection control.