Abstract: This paper designs a 16-channel data acquisition system based on the PCM-3350 PC104 embedded development platform, using the MAX1308AD conversion chip. The system boasts a maximum acquisition speed of 1Msps and a 12-bit resolution, capable of both channel scanning and single-channel acquisition. The focus of this design is the use of a CPLD as the main control chip to control the data acquisition card. Keywords: Embedded system, PC104, data acquisition, large-scale programmable logic device 1 Introduction With the development of science and technology and the economy, embedded systems have been widely applied in the home, industrial, commercial, communications, and defense markets. The PC104 is an embedded platform compatible with IBM PCs, offering flexible scalability. Its compact size is ideal for embedded system applications. Modern data acquisition demands high speed and high precision, requiring a powerful embedded platform, which the PC104 perfectly meets. This paper designs a 16-channel data acquisition system based on the PCM-3350 PC104 embedded development platform and using the MAX1308AD conversion chip. The system has a maximum acquisition speed of 1Msps, a resolution of 12bit, and is capable of both channel scanning and single-channel acquisition. 2. Data Acquisition System Design The data acquisition system mainly consists of an amplifier circuit, an optocoupler isolation circuit, a multiplexer, an AD converter with a sample-and-hold circuit, a clock circuit, a CPLD control circuit, and a data buffer (FIFO). The overall block diagram is shown in Figure 1: [align=center] Figure 1 Overall Block Diagram of Data Acquisition System[/align] 2.1 A/D Conversion Data Acquisition Circuit The A/D converter uses the MAX1308AD chip, which is a chip with a sampling rate of up to 1Msps, a resolution of 12 bits, and simultaneous sampling of up to 8 channels. It uses a +5V analog power supply and a +3V to +5V digital power supply. Its hardware system connection is shown in Figure 2: [align=center] Figure 2 MAX1308AD Hardware Connection[/align] 2.2 FIFO Storage Circuit The FIFO circuit uses the IDT7203 chip from IDT, a dual-port storage buffer chip with a 2048×9 storage structure and a 12ns... High-speed access time, simple structure, easy to operate, and has control terminal, flag terminal, expansion terminal and internal RAM array. The internal read and write pointers can automatically write and read data on the first-in-first-out basis. 2.3 CPLD Control Circuit Design The design of CPLD (EPM7160STC100-6) is the core of this acquisition system. It can decode the PC104 address bus and the generated logic control signals play a control role in the working state of each unit. Data can be read by polling. When the empty label of FIFO is valid, an interrupt is generated, causing the host to stop reading from FIFO. In the PC104 ISA part, the 16-bit data bus D[0..15] of ISA is used. A[0..9] is the address bus of PC104; IOW and IOR are read and write signals for the specified device; AEN is to enable DMA control address bus, data bus and read and write command line to perform DMA transfer and read and write to memory and IO devices. The system workflow is shown in Figure 3: [align=center] Figure 3 System Workflow[/align] The working logic block diagram of the data acquisition system is shown in Figure 4: [align=center] Figure 4 Logic Block Diagram of the Data Acquisition System[/align] Address decoding and controller: The A/D converter can only work when the address is selected, and the PC104 operates in 16-bit data bus mode. A0 to A3 control the selection of the conversion channel respectively; Start trigger: Used to control the start of A/D conversion, its operation is performed through write signals and CONVST signals; Interrupt response register: Used to query the interrupt caused by the FIFO being empty after A/D conversion is completed. Both the start trigger and the interrupt response register are located inside the status controller; Read data register: When the FIFO is not empty, the conversion result in the FIFO directly enters the data bus. Bits 12 to 15 are provided by the CPLD, making the data equal to it before entering the 16-bit data bus to complete the entire conversion process. 2.4 Address allocation of the acquisition card Since this data acquisition card works as a standard peripheral of the PC104. PC104 specifies that the operating address of the peripheral is A[9:0]. Address conflicts must be prevented in the system software design. PC104 uses address bits A0 to A9 to represent I/O port addresses, which can provide 1024 port addresses. The first 512 are used by the system board and the last 512 are used by the expansion slot. When A9=0, it represents the port address on the system board; when A9=1, it represents the port address on the expansion slot interface card[2]. Therefore, the board address of this acquisition is determined by A[9:3], and the offset address is determined by address lines A[2:0]. Selecting this address means the corresponding operation. After the CPLD decodes the address, it generates the corresponding control. For the board address, jumpers can also be set on the board for convenience. The base address allocation and decoding address allocation of the acquisition card are shown in Table 1. The address range of the data acquisition card designed in this paper is 2E0H-2F7H, and address conflicts will not occur. [align=center]Table 1: Address Allocation and Decoding of Data Acquisition Card[/align] 2.5 Other Circuit Design Since the MAX1308 contains multiple analog switches, two MAX1308 chips can be used for simultaneous sampling of 16 channels. In terms of hardware, to reduce latency and improve speed, the CPLD or FIFO and data acquisition section are integrated onto a single four-layer printed circuit board, which is then connected to the PC104 via connectors. The power supply section should separate the digital and analog power supplies. Considering the accuracy and stability of A/D conversion, 6N137 optocouplers are used for isolation. 3 PC104 Platform The PC104 platform hardware uses the PCM-3350 motherboard, a product designed with the PC/104 bus standard structure. It is a representative product of Advantech's new generation of high-speed, low-power PC/104 series. The controller module includes a main 32-bit microprocessor unit with 32MB of RAM and built-in non-volatile memory for data and program storage, providing VGA and LCD display interfaces. This module also features a series of standard communication ports, providing various communication methods, including serial communication (RS232, RS485), Ethernet, and a PC104 bus interface. 4. Software Design Since the PC104 CPU module supports read/write solid-state drives (SSDs), replacing conventional disk drives with semiconductor storage devices significantly improves system reliability and reduces power consumption and cost. In this system, based on the characteristics of SSDs, the operating system software uses DOS 6.22, with Tubor C 2.0 as the development environment. The application program is implemented using a combination of C and assembly languages. Furthermore, when writing the software, the base address of the I/O board must first be set, and then the addresses of other peripheral register ports, including read/write ports, control words, and channel selection addresses, are determined based on the base address. 5. Conclusion Data acquisition technology is an important component of information science and has been widely applied in various fields of national economy and national defense. With the development of science and technology, data acquisition technology has a broad prospect for development. This paper, based on the PC104 embedded platform and using the MAX1308AD conversion chip, designed a 16-channel data acquisition system with a maximum acquisition speed of 1Msps and a resolution of 12bit. Due to its small size and portability, this data acquisition system can be conveniently used in field operations. Furthermore, with the integration of PC104 into the embedded field, embedded system designers can use software compatible with desktop PCs. PC104 has been proven by many users to be an ideal solution in the embedded field, especially when combined with the PCI bus, it will be even more powerful. The development prospects of PC/104 are very promising, and the future of "stacked PCs" is infinitely bright. The author's innovation lies in concentrating the control signals of various circuit modules onto a single CPLD chip and adopting a flexible circuit design method, which enhances the flexibility and developability of the circuit design. References [1] Wayne WolF, translated by Sun Yufang et al. Embedded computing system design principles [M]. Beijing: Machinery Industry Press, 2002: 1-36. [2] Wang Shao, Lü Chao. Application of embedded computer module PC104 in engineering [J]. Optoelectronic Technology Application. 2003 (5): 48-50. [3] Zhang Pizhuang. Flexible design of data acquisition circuit in ultrasonic detection system [J]. Journal of Test Technology. 2005 (2): 226-229. [4] Shen Yu, Qi Wei, Zhang Yi. A method for implementing real-time high-speed data acquisition and storage system [J]. Microcomputer Information. 2006 (1): 83-85. [5] PC/104 Embedded Consortium, PC/104 Specification Version 2.5 [S], November 2003. [6] Xiao Zhongxiang, Meng Kaiyuan et al. Data acquisition principles [M]. Xi'an: Northwestern Polytechnical University Press, 2001: 1-10. Research and Implementation of a Data Acquisition System Based on PC104