Abstract: This paper introduces the implementation of a digital isolated I/O (Input/Output) module based on the CompactPCI bus. Through hardware and driver design, this module can realize digital signal transmission and isolation, playing a practical role in indoor testing systems. Keywords: Input/Output, PLX9030, Isolation Driver 1 Introduction 1 An important feature of the PCI bus is its extremely high data transmission speed, making it the standard bus for next-generation microcomputers. However, the gold finger card insertion method of PCI cannot meet the high mechanical strength requirements of industry. The CompactPCI specification, developed by PICMG, is fully compatible with the PCI standard in terms of electrical, logic, and software functions (see Reference 1 for PCI specifications). It provides a more robust and durable version of PCI for industrial and embedded applications, representing a new open industrial computer standard. The digital isolated I/O module based on the CompactPCI bus introduced in this paper is applied to indoor testing systems with high vibration resistance requirements. 2. Design of CompactPCI Bus Interface Currently, there are generally two methods for designing CompactPCI interface cards. The first method is to fully integrate the PCI interface into the ASIC. The advantages of this approach are high integration, low production cost for mass production, and the use of mature cores. The other method is to implement the CompactPCI bus interface controller in an FPGA based on the CompactPCI protocol. However, due to the inherent complexity of the CompactPCI bus protocol, achieving stable operation in the short term is very difficult. Considering project requirements, cost, ease of development, and subsequent development, the PLX9030 chip was chosen as the interface chip for the CompactPCI bus design. [align=center] Figure 1 Schematic diagram of PLX9030 control principle[/align] 2.1 PLX9030 Implementation of CompactPCI Bus Interface Design As shown in Figure 2, the design mainly consists of three functional parts: one is the interface control logic between the PLX9030 and the CompactPCI bus, another is the interface control logic between it and the local bus, and the third is the interface control logic with the CompactPCI configuration memory serial EEPROM. [align=center]Figure 2 PLX9030 Implementation of CompactPCI Bus Interface Control[/align] The PLX9030 interface control chip connects the CompactPCI bus and the local area bus, implementing all CompactPCI interface signals internally. This module's local area bus control unit is used for input/output gating control. It employs simple decoding, latching, and buffering to ultimately achieve individually controllable 16-bit data input and 16-bit data output. The control principle is relatively simple, and to save board space, a CPLD7128 is used. For design details, please refer to Reference 3. The interface control logic of the CompactPCI configuration memory serial EEPROM is the focus of the design. 2.2 Configuration Register The PCI specification stipulates that any PCI device must implement a certain number of configuration registers to provide necessary configuration information. The serial EEPROM corresponding to the 9030 needs to have a capacity greater than 2Kbit (128 words * 16 bits) and needs to have an address auto-increment function. In this project, the 93LC66 chip was selected. The PLX9030 provides a pin-to-pin interface corresponding to the serial EEPROM; simply connect the corresponding pins, as shown in Figure 2. For details on the registers that need to be configured, please refer to Reference 2. During power-up, the PLX9030's internal registers are reset by the RST# signal of the PCI BUS, and a response signal RETRY is given. The LRESET# signal is output on the LOCAL BUS to check if the serial EEPROM exists. If the EEPROM is installed, the PLX9030 begins reading the serial EEPROM. If the first word read is not FFFFH, the PLX9030 continues the read operation, using the value in the EEPROM to configure the on-chip registers; otherwise, the EEPROM is considered invalid and default values ​​are used. For the PLX9030, the first four bytes of the EEPROM should be 30H, 90H, B5H, and 10H, where 9030H is the device number and 10B5H is the manufacturer number. The PLX9030 uses the value in the EEPROM to configure the on-chip registers; otherwise, the default values ​​are used. 3. Design of Module Isolation Circuit Isolation refers to the use of methods such as transformers, optocouplers, or capacitors to transmit signals between the system under test and the test system, avoiding direct electrical or physical connections. Optocouplers transmit information based on the photoelectric conversion principle. They not only electrically insulate the information transmitting end (primary side) from the information receiving end (secondary side), thus providing strong suppression of ground potential difference interference, but also have strong suppression of electromagnetic interference. Furthermore, they are fast, inexpensive, and have simple interfaces, making them widely used. The primary side of an optocoupler is always a light-emitting diode (LED), but the secondary side has various structures, such as photodiodes and photocrystals. This card uses a high-speed CMOS optocoupler with a transmission rate of up to 10MHz, model HCPL2630. For a detailed explanation of the principle, please refer to reference 4. Its primary-to-secondary delay time is only 28 ns, thus its speed far exceeds that of ordinary optotransistor-type opto-isolators. The internal structure schematic is shown in Figure 3. The method for adding the opto-isolation circuit is shown in Figure 4. [align=center]Figure 3 Internal Principle of HCPL2630[/align] [align=center]Figure 4 Connection Diagram of Optocoupler[/align] Since the front end of the optocoupler is a light-emitting diode (LED), the maximum current cannot exceed 15mA, so a current-limiting resistor R must be added. The value of the current-limiting resistor R has a significant impact on the performance of the optocoupler. If R is too large, it will lead to a large pulse edge delay; if R is too small, it will easily damage the LED at the front end of the optocoupler and shorten the optocoupler's lifespan. Therefore, it is necessary to conduct repeated experiments to determine the final value. Due to individual differences in the devices, during the debugging process, some optocouplers were found to have insufficient driving capability after running for a period of time, requiring a reduction in the current-limiting resistor and an increase in the current to reliably turn on the LED. The input and output terminals of the optocoupler need to use different power supplies, so a DC5V-DC5V power isolation module with a built-in π-type filter was applied to the board. After adding a few external circuits, a very small output ripple can be achieved. 4. Hardware Principle of the Module As shown in Figure 5, when a digital signal is input from the J2 connector of the CompactPCI to the digital isolated I/O module, it first passes through an optocoupler isolator to ensure that the external signal does not cause voltage surges to other signals on the board; when the bus issues a read operation command, the PLX9030 and CPLD receive the read operation command, and the corresponding control bits send the isolated signal to the CompactPCI bus. [align=center] Figure 5 Hardware Principle of Digital Isolated I/O Module[/align] When a digital signal is output from the CompactPCI bus to the local bus, the corresponding control bits and data are first sent to the CPLD through the PLX9030. After the CPLD receives the command, it sends the corresponding data out through the optocoupler isolator and driver. External devices can be controlled as needed through the CompactPCI J2 custom pin. 5. WinDriver Device Driver Development (1) After opening the WinDriver application, the Driver Wizard appears. Select Create New Driver to display a list of all hardware cards in the current system, as shown in Figure 6. [align=center] Figure 6 List of all hardware cards in the current system[/align] Select the hardware device for which you need to build a driver from the list. For PCI devices, click the Generate.INF button to create the installation information file 1518.inf. Then modify some of the contents of 1518.inf according to the information required by the board. (2) Use Driver Wizard to generate application-level API functions for operating the hardware. Store them in the DIO.h file. (3) Start VC++6, create a DLL project, include some unit files generated by Wizard into the project, add code to complete specific tasks on this basis, use the API functions in DIO.h to complete DIO.c, and provide the calling interface for the application. (4) Write the interface unit file DIO.def, compile the project into a dynamic link library DIO.dll. The application can directly call this dynamic link library. Call the DIO.dll dynamic link library in the main test program to manipulate the digital isolated I/O module to run in conjunction with other modules. 6. Results and Discussion To date, the digital isolated I/O module based on this scheme has been successfully applied to an indoor testing system and has achieved mass production. The digital isolated I/O module is one of the important modules in a CompactPCI-based indoor integrated testing system. It can simultaneously realize the functions of both digital signal input and output, simplifying the selection of peripheral hardware and improving the system's versatility and scalability. Furthermore, opto-isolation measures are implemented for the input and output, achieving electrical insulation between the system and external devices, greatly improving the overall system's anti-interference performance. The module's design is versatile and can be applied to other CompactPCI bus systems. With the increasing application of the CompactPCI bus in the military and industrial fields, it has broad development and application prospects. The authors' innovations: The digital isolated I/O module realizes the functions of both digital signal input and output, simplifying the selection of peripheral hardware and improving the system's versatility and scalability; simultaneously, opto-isolation measures are implemented for the input and output, achieving electrical insulation between the system and external devices, greatly improving the overall system's anti-interference performance. References [1] Tom Shanley, Don Anderson, Addison Wesley, 2000 [2] PCIMG 2.0 D3.0 CompactPCI Specification September, 1999 [3] Song Wanjie, Luo Feng, Wu Shunjun, CPLD Technology and Its Application, Xi'an University of Electronic Science and Technology Press, 1999 [4] HP, Isolation Circuit Design Guide, 2000 [5] Zhou Duo et al., PCI Protocol Interface Design and Verification, Microcomputer Information, 2005.5. P194-195