Ethernet-based networking is one of the fastest-growing technologies in the industrial market. Most industrial Ethernet standards use the IEEE 802.3 standard Ethernet protocol, enabling these networks to transmit standard network services and real-time data. However, each standard employs different technologies to provide real-time performance; some use custom hardware, some utilize custom software, and others use fully standard Ethernet/TCP/IP implementations. This results in numerous incompatible standards with varying levels of performance and cost. A growing approach to addressing the non-deterministic communication time of the Ethernet protocol is to implement a local clock within each device. This approach is relatively easy to implement because most devices have microprocessors and (relatively) high-speed clocks. The only limitations of this method are communication latency and system-wide clock synchronization accuracy, provided that precise clock synchronization can be achieved and maintained across the entire network while controlling the precise timing of the entire system. This system control approach is unsuitable for applications such as precise motion control (e.g., precise control of motor speeds under constantly changing loads) because they require very short communication delays between the controller and devices. However, it is useful for precise control of entire systems requiring highly synchronized system-level control (e.g., speed changes), such as a large printing plant or a long automated production line. If there is sufficient time to issue a command to each device, the only constraint on the accuracy of this clock-based control is the system-wide clock synchronization accuracy. Several industrial networking standards (not just internet-based standards) are adopting the IEEE 1588 standard to provide this control capability. IEEE 1588 provides a highly accurate master clock and a proven clock synchronization mechanism that can be used to generate all local clocks and maintain very precise system-level synchronization with the master clock. Ethernet-based networks are favored due to their low cost and ease of implementation. Ethernet switches are key components that help leverage these advantages, and enterprise systems heavily rely on them for high-performance and easy-to-maintain infrastructure. This huge enterprise market for switches means they are easy to implement and inexpensive, but most switches currently on the market are not designed for low latency performance or deterministic routing time, making them difficult to use in industrial environments. The IEEE 1588 system synchronizes the clocks of the master and slave devices by detecting the communication delay between them. Placing a switch between the master and slave clocks introduces additional delay because the switch must analyze packets before routing them. This increased delay is not ideal, but it can be corrected, so it's not a major problem. The biggest issue is that as traffic increases, the time required to route packets increases dramatically. This is due to the time needed to buffer, analyze, and route packets to numerous destinations. This change significantly reduces the accuracy of 1588 clock synchronization, thus substantially degrading the real-time control performance of the entire system. Measuring the delay between the 1588 master and slave clocks also relies on the symmetry of communication times in both directions. This is because the measurement method involves counting the time it takes for a time-stamped message to travel from the slave clock to the master clock and back, and then dividing that time by 2. In most switch and Ethernet network implementations, this symmetry is unlikely to occur, further reducing clock synchronization accuracy. [align=center]Figure 1: Typical boundary clock application block diagram[/align] However, the IEEE 1588 standard provides a solution to this problem: if the switch itself also has a clock (as shown in Figure 1), the time required for packet routing can be measured and integrated into the synchronization calculation. Since the system does not require this functionality, switches containing such 'boundary' clocks are rare, and even when they are, they are generally expensive and typically custom-implemented for specific networks. With the rapid proliferation of IEEE 1588-based networks, manufacturers face a significant challenge in implementing IEEE 1588 functionality efficiently and cost-effectively in their products and network infrastructure. Developing custom ASIC solutions is possible, but with rising ASIC development costs and rapid changes in industrial Ethernet standards, such development is slow, risky, and uneconomical. Alternatively, a solution could be developed for each protocol using a microprocessor and third-party ASICs or ASSPs for specific network protocols, but this means implementing a separate solution for each network standard, which is also expensive and inefficient. These solutions may also suffer from a lack of flexibility and rapid obsolescence. Currently, designers can only circumvent these limitations by carefully implementing the network, minimizing the use of switches, or minimizing real-time network traffic. While such network isolation measures can achieve acceptable performance levels for some applications, they are difficult to implement or maintain. Saving Development Time Implementing an IEEE 1588-enabled switch using an FPGA is an ideal solution to this problem. Altera, National Semiconductor, and MorethanIP have collaborated to provide industrial Ethernet designers with an optimized eight-port switch design that can shorten engineering development time by six to nine months. This time saving will give equipment manufacturers a competitive edge in time-to-market. [align=center] Figure 2: Eight-Port Switch Development Board with IEEE 1588 Timing Control[/align] Figure 2 shows a MorethanIP Enterprise Systems development board with embedded IEEE 1588 functionality, based on Altera's Stratix II FPGA. The accompanying reference design implements an IEEE 1588-enabled switch in a simple, cost-effective manner and is easily modified to suit other systems and rapidly changing market demands. These advantages are achieved through the flexibility of the FPGA and the integration of a 32-bit RISC processor within the FPGA design. The Ethernet MAC core and switching matrix core intellectual property (IP) with 1588 timing control and programmable uplink functionality were developed by MorethanIP GmbH. MorethanIP Enterprise Systems also provides a UDP and 1588 software protocol stack that runs on a 32-bit AlteraNios II RISC processor soft core. To provide optimal physical interfaces, this eight-port switch design utilizes four dual-port PHY transceivers from National Semiconductor Enterprise Systems. The reference design features clock synchronization capability of less than 100ns, suitable for a variety of applications. This level of accuracy is critical for meeting the stringent communication latency and Quality of Service (QoS) requirements of industrial connectivity. Target applications include switches using various industry standards such as Ethernet/IP, ProfiNet, Ethernet Powerlink, and other Ethernet protocols. Extending product lifecycle: The programmability of the FPGA is key to the aforementioned design advantages. Starting from a single hardware platform, designers can easily implement switches supporting different industrial Ethernet protocols such as EtherCAT and ProfiNet. This development board supports different industrial Ethernet protocols within the same system or from the same Ethernet port. This is achieved by implementing different Media Access Controller (MAC) hardware modules and embedded processor software to support different Ethernet standards and IEEE 1588 functionality. The ability to easily reuse previous designs and the availability of off-the-shelf IP means that FPGA-based designs can generate a configuration supporting new features in a very short time compared to designs using ASIC or ASSP devices. The FPGA loads the hardware configuration and embedded processor software from a serial flash memory. During production and even after the device is delivered to the field, the FPGA's hardware and software functionality can be easily changed by rewriting the flash memory contents. The programmable hardware and software processing capabilities within the FPGA mean that designers can integrate the required additional functionality through applications that function as hardware or software. The ability to implement new features by simply reprogramming the FPGA guarantees the future of the product (such as support for IEEE 1588 v2.0) and allows for very rapid delivery of new features to customers. Because of the long lifecycle of FPGAs, device manufacturers do not need to worry about potential device end-of-life risks. Because the design is IP-based, porting it to next-generation FPGAs is relatively easy, allowing designers to potentially benefit from lower costs or higher performance in next-generation FPGA products. The ease of field upgrades further makes FPGA implementation the best approach for product development, ensuring support throughout the product lifecycle. This reference design uses Altera's Stratix II FPGA, allowing all Nios II processor code to be stored in on-chip memory; however, a lower-cost system can be implemented using Altera Enterprise Systems' Cyclone III series FPGAs. Figure 3 shows an embedded eight-port switching matrix from MorethanIP GmbH Enterprise Systems, containing eight 10/100Mbps MACs compliant with the Ethernet 802.3 specification. Each MAC supports IEEE 1588, meaning it can use a locally synchronized high-precision clock from a programmable timer to "time-stamp" each incoming 1588 data frame. [align=center]Figure 3: Block diagram of MorethanIP's eight-port switch conforming to the IEEE 1588 standard[/align] To implement boundary clock applications, the switch design simultaneously implements IEEE 1588 V1 master and slave applications. Ports communicating with the master are automatically configured as slave ports. The embedded 1588 application generates an accurate clock via the slave port and forwards this clock information to other ports automatically configured as master ports. Tight integration with programmable timers ensures that the clock is synchronized with the master clock within 100ns. Within the switch, each port can implement up to two priority queues to provide Quality of Service (QoS) guarantees for critical services. The switch can also identify and prioritize traffic by programming and utilizing a 3-bit VLAN priority field, a 6-bit DiffServ Layer 3 code point (IPv4), or an 8-bit service class (IPv6). The switch design supports IEEE 1588 version 1 boundary and version 2 transparent clock applications. The design can be further modified and enhanced to add customized logic, such as adding bridging application software to different system interfaces like traditional protocols or PCI, thus facilitating the integration of the switch into existing systems. [align=center] Figure 4: IEEE 1588 Block Diagram Including Software and Hardware[/align] In this design, the Nios II embedded processor supports IP configuration and management of the switch, and can run the User Datagram Protocol (UDP) stack, the IEEE 1588 protocol stack, and precise timing synchronization. It also supports PHY management and line diagnostics for dual 10/100 PHY transceivers (as shown in Figure 4). The embedded processor can also be used for higher-level networking functions, such as running Spanning Tree Protocol (STP) and Rapid Spanning Tree Protocol (RSTP) and terminating TCP/IP links. STP and RSTP are link management protocols that support path redundancy, preventing unwanted loops within the network (for an industrial Ethernet network to function properly, there can only be one valid path between two nodes). PHY Transceiver [align=center] Figure 5: Block Diagram of National Semiconductor's PHY Transceiver [/align] Each transceiver has two completely independent 10/100Mbps ports for multi-port applications, as shown in Figure 5. The transceiver's port switching also allows the two ports to be configured to provide fully integrated range extension, media conversion, hardware-based failover in the nanosecond range, and port monitoring. This device integrates multi-port support for common industrial Ethernet topologies. In particular, designers need redundancy support for different applications and the ability to handle failover under various conditions. Switching from one network stack to another can take several hundred milliseconds, but some applications (such as security applications) require extremely fast failover, ideally implemented at the PHY layer. The transceiver in this reference design switches from one port to another in the nanosecond range, even while the host still manages the control path. Architectural improvements in the transceiver signal path enable performance far exceeding minimum PHY layer specifications, completely resolving design issues such as jitter and latency. Each Ethernet PHY layer is driven by a reference clock. To minimize jitter, the PHY layer specification requires an extremely precise clock, with an accuracy within 50 PPM of the transceiver's 25MHz reference clock. Furthermore, to meet specification requirements, the initial jitter must be very small. To address this, a mechanism tolerating larger jitter is integrated into the architecture. The device architecture also optimizes latency performance for real-time Ethernet operation to ensure minimal switch latency. In many real-time system implementations, Ethernet packet data transmission latency is a critical parameter for normal system operation, and the fixed or variable transmit or receive latency within the Ethernet PHY becomes a significant component of system latency calculations. The PHY transceiver is designed to limit variations in receive data latency, thus providing highly deterministic system latency. Because the received data is aligned with the receive clock, the nondeterministic factors typically encountered during data reception are avoided. Therefore, the device can provide highly deterministic receive data latency in both MII and RMII modes. Additionally, the transceiver reduces the nondeterministic possibilities commonly found in transmit RMII latency. Another important design feature is the built-in cable diagnostics, which adds proactive diagnostic capabilities to the traditional Time Domain Reflectometry (TDR) method used in transceivers. The innovative fault isolation function leverages the transceiver's powerful signal processing capabilities to track link quality while data is being transmitted. This highly robust TDR implementation sends pulses from either the receiving or transmitting wire pair and observes the results on both pairs. By observing the type and intensity of the reflected signal on each pair and calculating through software, the cable's short-circuit and open-circuit conditions, the distance to the fault point, which pair is problematic , and pair misalignment can be determined. Proactively monitoring and correcting changing or deteriorating link quality reduces system downtime and saves on costly repairs. This feature can also detect faults that occur during installation, saving significant commissioning time. Industrial Ethernet technology is constantly evolving and becoming increasingly prevalent, while designers face a growing demand for cost-effective industrial switches. ASIC- and ASSP-based switches, due to their fixed architecture, offer virtually no room for customizing new system features. Adding features typically requires a complete redesign, resulting in additional design time and costs. However, as mentioned above, FPGA designs that support IEEE 1588 switches can save 6 to 9 months of engineering time and provide designers with the flexibility they crave, helping them implement Precision Timing Protocol (PTP), support multiple industrial Ethernet standards, additional standard interfaces, or other possible custom features.