Abstract: This paper designs a stepper motor control system based on CPLD. It uses CPLD as the core device, which greatly reduces the use of peripheral components. It has the advantages of good system expansion performance, high reliability, strong anti-interference ability, simple structure, low cost, no CPU time occupation, and easy high-speed control. Keywords: stepper motor, controller, CPLD 1. Introduction Stepper motors can achieve speed regulation, fast start and stop, forward and reverse control by changing the pulse frequency in a wide frequency range. The open-loop system composed of them is simple and reliable. Therefore, it is widely used in CNC machine tools, automatic recorders, industrial robots, non-destructive testing and other systems. The performance of stepper motors largely depends on their control system [1]. The stepper motor control system based on CPLD [2] has the characteristics of multiple I/O ports and free programming to define its functions, which greatly reduces the size of the circuit and improves the stability of the circuit. Advanced development tools greatly shorten the design and debugging cycle of the entire system. Using VHDL language for software programming, and using EDA design software to compile, optimize, synthesize, simulate and adapt the program, digital input can be realized for stepper motor control. The system's peripheral circuit design is relatively simple and reliable. Given the characteristics of CPLD and VHDL, the system has good scalability and a certain degree of versatility in control systems. 2. System Design Scheme As shown in Figure 1. First, the original clock signal is input, which is divided by a frequency divider to obtain a 10ms button judgment period and a clock signal with a frequency of 2048Hz. The 2048Hz signal is then divided by external hardware and input to the chip as the motor's speed signal. Four control signals are input via buttons, and together with the motor's speed frequency signal, they are sent to the motor control state machine. The state machine selects the motor output control signal based on different inputs. [align=center] Figure 1 System Design Block Diagram[/align] 3. System Hardware Design The CPLD uses Altera's MAX7000 series EPM7128SLC84-15. The drive circuit schematic is shown in Figure 2. [align=center] Figure 2 Drive Circuit Schematic[/align] The CPLD output control signals are connected to ports A, B, C, and D in the figure. These control signals are opto-isolated before entering the ULN2003A. The ULN2003A is a chip integrating seven Darlington transistors. A 5V high-level signal from the optocoupler passes through the ULN2003A, and its output is connected to ground. The positive terminal of the stepper motor is connected to a 12V operating voltage, and the negative terminal is connected to the output of the ULN2003A. When the CPLD's I/O port is low, the negative terminal of the stepper motor is open to ground, there is no voltage difference between the positive and negative terminals, and the motor does not run. When the CPLD's I/O port is high, the negative terminal of the stepper motor is connected to ground, a 12V voltage difference is formed between the positive and negative terminals, and the motor runs. The stepper motor's speed is determined by the energizing speed of the four coils, which is determined by the frequency of the input pulses. Therefore, selecting the stepper motor's speed is essentially selecting the frequency of the input pulses. This design uses a dual four-bit binary counter 74LS393N for hardware frequency division. The frequency source is the 2048Hz frequency of the CPLD. By connecting the T flip-flops inside the 74LS393N in series, the 2048Hz frequency can be divided to obtain frequencies from 0.5Hz to 1024Hz with a ratio of 2. These frequencies can be selected by a hardware selector and input to the CPLD's I/O port to control the motor speed. 4. Software Design This design uses Quartus II for system software design and simulation. Quartus II is an FPGA/CPLD development integrated environment provided by Altera, supporting the VHDL hardware description language. First, four control pulse signals—RST (reset), EN (enable), MODE (mode), and CTRL (direction)—are generated by external buttons. These pulse signals are debouncing through a debouncing module before being sent to the main controller. Since the EN, MODE, and CTRL signals are active-level within the main controller, a T flip-flop is used to lock the level before the signals are sent to the main controller. Four control signals and the externally input motor speed clock signal clk_step are sent to the main controller. After processing, the main controller obtains the energizing signals for the four phases of the motor. The energizing signals are then eliminated by D flip-flops and sent out from the chip's I/O port. The main controller module has 5 input signals and 4 output signals. Its main internal structure is a bidirectional Moore-type state machine, and its main code is as follows: library ieee; use ieee.std_logic_1164.all; entity zhuangtai is port（ en,clk,rst,mode,ctrl: in std_logic; ——EN is the enable signal, RST is the reset signal, MODE is the motor operation mode signal, and CTRL is the forward/reverse control signal. These four signals are active level; CLK is the motor speed frequency. a,b,c,d: out std_logic）; ——A,B,C,D are the energizing signals for the four phases of the stepper motor. The architecture zt1 of the stepper motor is type states is (statex, state0, state1, state2, state3, state4, state5, state6, state7); — state0-state7 represent the different energized states of the stepper motor, while statex represents the de-energized state. signal ste:states; signal q:std_logic_vector(3 downto 0); — Q is the four-phase output signal, with A, B, C, and D corresponding to bits 3, 2, 1, and 0 of Q, respectively. The stepper motor can operate in four-phase or eight-phase energized states. For considerations of torque, smoothness, noise, and reduced angle, an eight-phase energized sequence is often used, i.e., A-AB-B-BC-C-CD-DA-A, as shown in Figure 3. [align=center]Figure 3 State Transition Sequence[/align] The state machine works as follows: When the rising edge of the speed clock clk-step arrives and EN is high, the state machine transitions between statex, state0-state7 according to different MODE and CTRL values. Finally, it assigns a value to the signal q based on the current state ste, and then assigns the high and low bits of q to the motor coil energizing signals A, B, C, and D respectively. begin moore: process (clk, rst) begin if rst='1' then ——If the reset signal is high, the reset is valid ste <= statex; elsif (clk'event and clk='1') then if en='1' then ——When the enable is 1, i.e., when working is allowed case ste is when statex => ——After judging the current state, first enter the corresponding judgment statement based on the current forward and reverse rotation signals, then judge the current operating mode signal, and after the judgment is completed, enter the corresponding next state. If ctrl='0' then if mode='1' then ste <= state0; elsif ctrl='1' then if mode='1' then ste <= state6; … 5. Conclusion The system function simulation is shown in Figures 4 and 5. The signals in the figures are defined as follows: clk: 12M clock signal, clk_step: stepper motor speed clock signal; EN: button enable signal, RST: button reset signal, MODE: button operation mode signal, CTRL: button operation direction signal. When MODE=1 and CTRL=0, the motor operates in the forward, eight-step conduction state; when MODE=1 and CTRL=1, the motor operates in the reverse, eight-step conduction state; the motor can also be controlled to operate in four-step conduction mode, in which case MODE=0. A, B, C, and D are the stepper motor four-phase coil energizing signals. [align=center] Figure 4 Simulation diagram of operation mode function 5 Simulation diagram of forward and reverse control function[/align] The innovation of this paper: Compared with the traditional design, this design module has a high degree of integration. The designed drive circuit is small in size, fast in speed, low in power consumption and stable in performance. It can select the appropriate motor control strategy according to different occasions, and the control is simple and convenient. This driver can be used wherever stepper motors are used. It has achieved good results in actual use, and the project has economic benefits of more than 5 million yuan. References: [1] Chu Rongzhen, Zhou Xiangning et al. Control and implementation of embedded stepper motor system [J]. Microcomputer Information, 2007, 23-1:53-55. [2] Ma Hongwei. Development of high performance stepper motor control system [M]. Xi'an: Xi'an University of Science and Technology Press, 2004. [3] Zhu Zhengwei. EDA technology and application [M]. Beijing: Tsinghua University Press, 2005.25-30