Abstract: This paper introduces a hardware design method for a 4-axis motion control card using the PCI dedicated interface chip PCI9052 as the interface bridge between the PCI bus and the motion control chip MCX314as. First, the overall structure of the motion control card, the PCI bus interface specification, the local bus interface circuit, and the signal interface circuit of MCX314as are given. Then, the configuration method of dual chip selection in the ISA mode of the PCI9052 board is given. Finally, the method of developing WDM driver using DriverStudio is given. Keywords: motion control card; PCI9052; PCI bus; MCX314as; WDM 1. Introduction This project is used for the four-axis control of the pick/placement head of the boom-type chip mounter (also known as the arch-type chip mounter) in cooperation between South China University of Technology and Guangdong Fenghua Group. The X and Y axes are horizontal plane movement, the Z axis is the pick/placement head pick-up and chip placement direction movement, and the U axis is the chip angle adjustment direction rotation movement [7]. According to project requirements, the MCX314as was adopted as the motion control core. The host computer only needs to write motion parameters into the MCX314as registers. Various complex motion control and interpolation calculations are all completed by the MCX314as, greatly improving the calculation and control speed. Communication with the computer is achieved through the PCI9052 as the PCI bridge interface, realizing 4-axis servo/stepper motor control, realizing position, speed, acceleration control, and linear and circular interpolation functions. 2. Hardware Structure of the Motion Control Card The hardware structure of the motion control card mainly consists of the PCI interface chip PCI9052, the motion control chip MCX314as, and corresponding optocoupler isolation, differential transmission, and other circuits, as shown in Figure 1. In this figure, DB represents the data bus, AB represents the address bus, CB represents the control bus, axis outputs are the output pulses of the four axes, and I/O refers to input/output control signals, etc. 2.1 PCI Bus Interface The PCI local bus is a high-performance, low-cost, open bus independent of the processor. Its advantages have led to its rapid popularization and development, and it has become the de facto bus standard for microcomputers. It is also widely used in embedded computers and industrial control computers. It can be divided into two types: 32-bit data/address multiplexed bus and 64-bit data/address multiplexed bus. The bus speed is divided into two types: up to 33MHz and 66MHz. The data transfer speed can reach up to 528MB/s [2]. We use a 32-bit bus with a speed of 33MHz. At present, the solutions for implementing the PCI interface can be divided into two types: using CPLD and using dedicated chips. Using CPLD to implement the PCI interface is more flexible, but it is complicated to implement. Using dedicated chips can reduce the design difficulty and shorten the development time. Therefore, we use the PCI9052 dedicated chip from PLX to implement the PCI bus interface. The bus interface is described in reference [1] (page 21). [align=center] Figure 1: Overall design of PCI card[/align] PCI9052 is a high-performance, low-cost PCI bus slave mode interface chip launched by PLX for expansion adapter cards. The chip pins can be directly connected to the gold fingers of the adapter card. The names and functions of each pin can be found in its DATASHEET[1]. The local bus is connected to the data lines, address lines, control lines, etc. of the MCX314as. The main features of the PCI9052 chip are as follows: (1) It conforms to the PCI2.1 specification and supports simple ISA to PCI bridge conversion; (2) It supports local bus to memory and I/O mapping; (3) The PCI interrupt signal is generated by two interrupt signals LINTI1 and LINTI2 of the local bus; (4) The clocks of the local bus and the PCI bus run independently of each other and are compatible with high and low speed devices. The operating clock frequency range of the local bus is 0 to 40 MHz; the operating clock frequency range of the PCI is 0 to 33 MHz. (5) The operation of the local bus can be changed through the configuration of the EEPROM, and multiplexing and non-multiplexing 8-bit, 16-bit and 32-bit general local buses are supported; (6) Serial EEPROM interface, the connected serial EEPROM is used to store important information such as device ID and local bus configuration; [1] 2.2 Local bus interface circuit The circuit connecting PCI9052 and MCX314as is shown in Figure 2: [align=center] Figure 2: PCI9052 and MCX314as connection[/align] MCX314as is an integrated circuit for implementing 4-axis motion control. It can control the position, speed and interpolation of 4-axis driven by stepper motor driver or pulse servo motor [3]. All its functions are controlled by specific registers. Motion control can be achieved by setting the registers. Its level is compatible with PCI9052 and can be directly connected. Based on the characteristics of the MCX314as itself, the PCI9052's local bus adopts a non-multiplexed 16-bit data bus ISA mode. Grounding the PCI9052's MODE (pin 68) enables non-multiplexed mode. The register configuration for ISA mode is detailed in Chapter 3. In the PCI9052's ISA mode, LRESET is positive logic, while the MCX314as's reset signal is negative logic; therefore, they must be connected via an inverter. BUSY# and INTN# should be pulled high with resistors to expedite data transmission and recovery after interruptions. 2.3 MCX314as Signal Interface Circuit The MCX314as is the core of the motion control card. Operations on its eight control registers and eight status registers enable speed, position, and interpolation control of four axes. Figure 3 shows the connection diagram for a single-axis drive system. The four-axis system is similar; each axis can use the same design. [align=center]Figure 3: MCX314as Drive System[/align] The MCX314as output drive pulses in two forms: one is a positive/negative pulse form. Taking the X-axis as an example, when XPP outputs a pulse, the X-axis rotates in the positive direction, and when XPM outputs a pulse, the X-axis rotates in the reverse direction. The same applies to all four axes. The other is a pulse/direction form. Taking the X-axis as an example, the XPP pin is multiplexed as PLS as the pulse output pin, and XPM is multiplexed as DIR as the direction signal output. The output form can be selected by setting bit D6 of register WR2. To match our motor driver, we chose the positive/negative pulse (CCW) form, using differential output to improve the transmission distance. The feedback encoder signal is transmitted differentially and isolated by high-speed optocouplers before being connected to the encoder input port of each axis. The encoder input signal can also be divided into two-phase pulse input (nECA, nECB) and up/down pulse input (PPIN, PMIN). Setting bit D9 of WR2 can select the pulse counting method compatible with the encoder. Each axis of the MCX314as has 8 I/O signals. Four output bits (OUT4-7) for each axis can be used as drive status indicators or as general-purpose outputs. Register WR3's D7 is used to set whether it is used as a general-purpose output. The 8 input bits can be used as positive/negative limit signals, position indication, alarm signals, etc. The I/O signals are level signals and can be isolated from the motor driver via optocouplers. 3. Configuration of the PCI9052-based Board By setting the PCI9052's configuration registers, it can operate in multiple modes, such as C mode, J mode, and ISA mode. Each mode corresponds to a different local bus operating mode and follows different bus specifications. The PCI9052's configuration information is stored in the connected EEPROM. Correct configuration determines whether the motion control card can function properly, so it is very important. Configuring the 9052 is a key focus of this design. 3.1 The data configuration local bus is a 16-bit ISA bus, compatible with the MCX314as, and can be directly connected. It only involves I/O signals, occupying chip select 3 (CS3#) of the local bus, as shown in Figure 2. Additionally, a 64KB RAM is connected for other purposes, unrelated to the motion control card; it involves memory signals and occupies chip select 2 (CS2#). In ISA mode, there are no actual chip selects 1 and 2. The card's EEPROM configuration information table is as follows: The table above shows the configuration data; registers not listed are set to 0. PLX's vendor ID is 10B5H, and the device ID is 9052H. The classification number indicates the type of bridge and the current version; for PCI9052, it is 02h. The subsystem ID and sub-manufacturer ID are 9052H and 10B5H respectively. PCI9052 only supports INTA#, so PCIILR (PCI interrupt register) D8=1 or D8=0 does not use interrupts. The PCI9052 has four local address spaces, from 0 to 3. Space 0 must be configured as a memory space and space 1 must be configured as an I/O space. According to the PCI9052 DATASHEET reference [1], space 0 is configured with FFFF0000H, with a space range of 64KB. D0=0 indicates that it is configured as a memory space. The base address in the table is 04000000H, and chip select 2 (CS2#) is used. Space 1 is configured with FFFFFFF1H, with an I/O space range of 16 bytes. D0=1 indicates that it is configured as an I/O space. Whether the two chip select pins (CS2#, CS3#) multiplexed in ISA mode output is determined by the base address of chip select signal 2 and the base address of chip select signal 3, respectively. D0=1 of the chip select signal base address enables chip select. The chip select base address is determined by the base address of space 1 or 0 plus the range of the configured space address. If the range is exceeded, the chip select will not output. The local address space 0 or 1 bus region is described as 00400022H and 0040003AH, which are identified as a 16-bit local data bus. The interrupt control and status register is 00001000H, interrupts are not used, and its D12=1 indicates that the local bus is in ISA mode. The control register determines the input/output functions of its various multiplexed pins, as well as the initialization control. Using an EEPROM containing the above configuration data to boot the board, the computer will allocate 16 I/O ports (03000000H-0300000FH) and 64K bytes of memory space (04000000H-04010000H). 3.2 Precautions for Selecting and Configuring EEPROM 1) The following signals are used for serial EEPROM connection: clock signal (EESK), read data signal (EEDO), write data signal (EEDI), and chip select signal (EECS). 1) The clock signal (EESK) is obtained by dividing the PCI bus clock by 32. 2) The selection of the EEPROM should follow the recommendations on the PCI9052 or a compatible 1Kbit EEPROM with continuous read functionality. 3) Online hot configuration (configured online via PCI9052) can be used. Software options include PLX's own PLXMON or JUNGO's WinDriver. The author used WinDriver v6.02, with the program PLX 9050 Diagnostics in the Samples directory of the software installation to read and write the EEPROM. This method is convenient, but sometimes read/write errors occur. Alternatively, a programmer can be used to write the configuration data to the EEPROM. This method is highly reliable, but repeatedly inserting and removing the EEPROM during experiments is inconvenient. 4. Driver Development: The ISA bus address space needs to be mapped to I/O space or memory space. To obtain the dynamically allocated mapping base address from the PCI bus configuration register and to read and write to the mapped port, a driver program must be written. A simple implementation of the driver can be achieved by using JUNGO's WinDriver to generate the driver. However, the driver generated by WinDriver is not efficient and can only be used for one month without a registration code. Therefore, we use DriverStudio plus WIN2000DDK to develop the driver. Under the wizard of DriverStudio, we input the device ID, manufacturer ID, classification number, and subsystem ID/submanufacturer ID to generate the framework of the driver, and then write the required program code. For information on the installation of the driver and its calling in the application, please refer to reference [5]. 5. Conclusion Practice has proven that the motion control card developed using PCI interface chip and dedicated motion control chip has a short development cycle, strong practicality, and high reliability. The hardware debugging and driver writing of this motion control card have been completed. Currently, some motion control functions have been completed, and application development is underway. References [1]. PLX Technology. PC I9052 data book. Printed in U SA, September, 2001. [2]. Tom Shanley (USA), Don Anderson (USA). Translated by Liu Hui et al. PCI System Architecture (4th Edition). Beijing: Electronic Industry Press, 2000.7 [3]. MCX314As User's Manual Ver1.0 2004-8-10. [4] Walter Oney (USA). Microsoft Windows Driver Model. http://www.oneysoft.com [5]. Wu Anhe et al. Windows 2000/XP WDM Device Driver Development (2nd Edition). Electronic Industry Press, 2005-02-01. [6]. Tao Jili, Lu Wuyi. PCI9052 and its application in the design of general network control cards. Microcomputer Information, 2003 Vol.19 No.3 P.72-73. [7]. Yuan Peng. Design and Implementation of Vision-Based Motion Control System for High-Speed ​​and High-Precision Chip Placement Machine [C]. Computer Integrated Manufacturing Systems, 2004, 12(10).