Abstract: This paper designs and implements a high-speed data acquisition system based on the PCI bus, mainly including analog input, acquisition, data transmission and storage, and computer interface. This system can be used for real-time high-speed acquisition of radar signals, and its performance and indicators meet the requirements. Keywords: High-speed data acquisition, A/D conversion, PCI bus 0 Introduction High-speed data acquisition systems, as the foundation of modern signal processing and information processing, have seen significant development in recent years with the continuous introduction of new A/D devices. However, the high price of general-purpose high-speed data acquisition systems is prohibitive. Therefore, finding a user-friendly A/D conversion device and obtaining a high-performance high-speed data acquisition system through simple circuit design has always been a goal pursued in engineering design. This paper introduces a high-speed data acquisition system that can acquire data from general radar frequency signals and implements a microcomputer interface for convenient post-processing of the acquired signals. 1 System Functions and Structure This system is based on radar frequency signal acquisition, and its design specifications are as follows: a. Data acquisition accuracy is 12 bits, and the data sampling rate is 10MHz; b. Flexible signal preprocessing configuration, capable of accommodating various forms of analog signal input; c. High-speed interface with computer via PCI bus; d. High-speed, large-capacity buffer; e. System control logic is completed by CPLD; f. Stable and reliable system; From a signal processing perspective, 10MHz speed basically meets the requirements of most radar signal processing; 12-bit accuracy is sufficient to guarantee radar signal processing, such as the requirements of moving target detection. The system structure block diagram is shown in Figure 1: [align=center] Figure 1: System Structure Block Diagram[/align] The system mainly includes several parts such as buffer amplification, A/D conversion, data latch, FIFO buffer, PCI bus control, and CPLD control. 2 Buffer Amplification and A/D Conversion Analog signal preprocessing is an important factor affecting system performance. Two aspects must be considered during design: 1. Ensure signal quality, improve the signal-to-noise ratio, and minimize distortion. 2. Transform the signal to an amplitude suitable for ADC processing and provide sufficient drive capability. Considering the high-speed and high-precision technical specifications, using Analog Devices' AD8011 as a high-resolution ADC buffer is a suitable choice, as it features fast settling time, wide bandwidth, low distortion, and high gain per unit bandwidth. The AD9220 is a high-performance, single-supply 10MHz, 12-bit analog-to-digital converter manufactured by Analog Devices Company (AD). It employs a novel architecture using low-cost, high-speed CMOS processing technology to achieve high conversion speeds with low power consumption. It is a complete monolithic ADC circuit with an on-chip high-performance, low-noise track/hold amplifier and a programmable voltage reference. To meet the requirements of DC accuracy and temperature drift in applications, an external reference source is also allowed. The AD9220 features a four-stage pipelined architecture and output error correction to ensure a 10MHz sampling rate and 12-bit accuracy across the entire operating temperature range without code loss, and also includes a one-bit overflow flag. Furthermore, the monolithic architecture improves reliability, thereby enhancing system reliability and reducing design costs. The schematic and timing diagram of AD9220 are shown in Figures 3 and 4: [align=center] Figure 3: AD9220 Schematic[/align] [align=center] Figure 4: AD9220 Timing Relationship[/align] 3 PCI Bus Controller In a microcomputer-based data acquisition and processing system, the computer interface card is a key hardware device. However, due to the complexity of the PCI bus protocol, designing a PCI interface card is a very difficult task. But if a dedicated PCI interface chip is used, the design can avoid the complex PCI bus protocol, greatly shortening the system development cycle. The PCI bus is an AD/C/BE# multiplexed bus. It uses a master-slave bidirectional handshake to control data transmission, and its interface circuit design is not much different from the design of traditional bus interface circuits. Generally speaking, a PCI interface circuit should perform the following functions: a. Address decoding and command decoding. b. Address generation circuit. c. Control signal generation. AMCC's S5933 bus controller is a powerful and flexible bus control chip. It conforms to the PCI Local Bus Specification version 2.1 and can function as a PCI bus slave to fulfill basic data transfer requirements; it can also function as a PCI bus master to access other PCI bus devices. The S5933 boasts a peak data transfer rate of up to 132 MB/s. The S5933 provides three physical bus interfaces: PCI bus interface, ADD-ON bus interface, and external configuration memory interface. Data transfer can occur between the PCI and ADD-ON buses, or between the PCI bus and an external configuration register. Data transfer between the PCI and ADD-ON buses can be achieved through three channels: the Mailbox channel, the FIFO channel, and the Pass-Thru channel. The S5933 provides two separate FIFO data channels, respectively for data transfer from PCI to ADD-ON and from ADD-ON to PCI. Both FIFOs support PCI bus master operation and support burst data transfers. In this system, we utilize the S5933's ADD_ON TO PCI FIFO channel to initiate the S5933's bus control function via the ADD-ON bus. The depth of the S5933's internal FIFO can be increased by adding external cascaded FIFO buffers. The external FIFO chosen is the IDT732653 from IDT. The ADD-ON interface is set to synchronous transmission with a clock of 33MHz. The first-in, first-out buffer in the system uses the IDT723653, a single-chip, high-speed, low-power CMOS bidirectional FIFO. This FIFO's dual-port clock can be synchronous or asynchronous. Transmission control is implemented using the ALTERA EPM7128 to control the data transmission logic. S5933 initialization is automatically loaded from the configuration memory during the system configuration cycle; in this system, we use a parallel 29C512 memory as the S5933's configuration memory. 4. Control Block and CPLD Design The system timing simulation is shown in Figure 5: [align=center] Figure 5: System Simulation Timing Diagram[/align] Wherein, WRFULL is the S5933 internal FIFO full signal, active high. BPCLK is the S5933 buffer clock output. AF is the FIFO programmable ALMOST FULL signal, active low. AE is the FIFO programmable ALMOST EMPTY signal, active low. In this design, the S5933 internal FIFO write uses synchronous operation, therefore WRFIFO enables the S5933 internal FIFO write. LE1 is the latch 1 clock, LE2 is the latch 2 clock, and OE enables the LE1 and LE2 latch outputs, active low. CLKA, CLKB, and ADCLK are the FIFO PORTA and PORTB clocks and acquisition/conversion clock outputs, respectively. FIFOENA and FIFOENB are the FIFO port A and B write and output data enable, respectively. In this design, the two ports of the external FIFO operate on different clocks. The specific data transmission is implemented as follows: Port A's clock is synchronized with the A/D conversion clock. After every two conversions, the data is latched by latches LE1 and LE2 and then sent to the FIFO via enable OE and FIFOENA. Port B's clock uses BPCLK. When AF is valid and WRFULL is invalid, the FIFOENB and WRFIFO signals are enabled. The external FIFO writes data to the S5933 until WRFULL or AE is valid. In this system, the entire data transmission is performed via DMA to transfer data to system memory, without CPU intervention, and is entirely implemented in hardware, improving data transfer efficiency. To fully utilize the bus bandwidth and improve the PCI data transfer rate, two 16-bit data latches are used to combine the A/D converted data into 32-bit data. After being buffered by the FIFO, the data is sent to memory by the PCI interface chip AMCC S5933. 5 Conclusion This system is suitable for radar signal acquisition and processing systems. It utilizes the high-speed characteristics of the PCI bus to realize real-time data acquisition, transmission and storage, effectively solving the problems of data transmission and storage in high-speed data acquisition systems. Its various performance indicators meet the requirements of radar signal processing. References: [1] Shen Lansun. Principles and Applications of High-Speed ​​Data Acquisition Systems. Beijing: Electronic Posts and Telecommunications Press, 1995 [2] Tom Shanley, Don Anderson, Liu Hui et al. PCI System Architecture. Beijing: Electronic Industry Press, 2000.7 [3] AMCC S5933 Data Book [4] ALTERA Product Manual [5] AD9220 Data Book