Abstract: This paper introduces the application prospects of embedded system development for multimedia, the MPC823e embedded controller chip based on the PowerPC core, and a hardware platform design for developing multimedia functions of the MPC823e. Keywords: Embedded system, MPC23e, hardware development platform 1. Introduction Embedded computer technology is one of the two important development directions of the 21st century. Embedded computers can be applied to consumer electronics (mobile phones, PDAs, digital cameras, digital TVs and IP phones, etc.), information appliances, communication equipment (routers, switches, firewalls, VPNs, etc.), industrial control and military electronics. It is estimated that in the next ten years, 95% of microprocessors and 65% of software will be used in various embedded electronic devices, supporting increasingly higher functional density, flexible network connectivity, lightweight mobile applications and multimedia information processing. The hardware platform of the MPC823e embedded multimedia information terminal described in this paper has rich peripheral interfaces and multimedia functions, realizing functions such as telephone service, broadband Internet access, email sending and receiving, electronic payment, broadcast advertising, and urban life services. 2. Introduction to MPC823e The PowerPC823e is one of Motorola's PowerQUICC series of embedded communication processors. Based on a Reduced Instruction Set Computing (RISC) architecture, it integrates a 32-bit microprocessor and various peripheral interfaces, possessing powerful communication and network protocol processing capabilities, and is widely used in multimedia and network products. Its functional structure mainly includes: an embedded PowerPC core, a System Interface Unit (SIU), a Communications Processor Module (CPM), and an LCD controller unit. Its system architecture block diagram is shown in Figure 1. [align=center] Figure 1 MPC823e Architecture Block Diagram[/align] As can be seen from the figure, the Communications Processor Module (CPM) supports 7 serial channels, including: 2 Serial Communication Controllers (SCCs), 2 Serial Management Controllers (SMCs), 1 USB interface, 1 I2C interface, 1 Serial Peripheral Interface (SPI), and 1 LCD control interface. Therefore, the MPC823e, through flexible programming methods, supports Ethernet, USB, T1/E1, and various communication protocols such as IEEE 802.3/Ethernet, UART (synchronous/asynchronous), and HDLC. In addition, the MPC823e features enhanced on-chip emulation and debugging capabilities, a full range of interface units, and interrupt control with priority programming. This system is based on these features of the MPC823e for the hardware design of the multimedia development platform. 3. System Hardware Overall Design The underlying design of the MPC823e multi-functional multimedia development platform requires comprehensive communication interfaces, sufficient memory capacity, debugging functions, and test display functions. According to the design, this system mainly consists of a host system, a storage system, a human-machine interface, and machine-to-machine interface circuits. The host unit design mainly includes the system power supply, PLL power supply circuit, clock circuit, hardware and software reset circuits, power-on reset circuit, MPC823e bus signal allocation and definition, etc. To enhance bus driving capability, the 74LVC245 chip is specifically selected. The type of memory used in the storage system depends on the microprocessor's support. The PowerPC series basically supports EDO, EPROM, FLASH, SDRAM, SPAM, etc. The capacity mainly depends on the kernel image, file system, and user application size. The communication interface circuit includes a human-machine interface and a machine-to-machine interface, providing one Ethernet interface, one RS232 interface, one USB interface, one I2C interface, and one 800x600 LCD interface. Meanwhile, based on the characteristics of this multimedia information terminal product, in order to communicate with the network management center and security module and implement keyboard functionality, a serial port chip ST16C552 was added. The ST16C552 has two standard RS232 serial ports. Simultaneously, through the PCMCIA interface (IP_B0～IP_B7) of the MPC823e and the printer parallel port of the ST16C552, the keyboard function is implemented using the principle of row and column scanning keyboard, supporting up to 8x12 keys, depending on the required number of keys. The connection diagram of the ST16C552 serial port chip and its connection with the MPC823e is shown below: [align=center]Figure 2 Connection diagram of ST16C552 and MPC823e[/align] In addition, the MPC823e also provides a BDM debug port, a test port, and an interface for connecting a speaker from the SPKROUT (B7) pin of the MPC823e. Finally, the CPLD circuit section was omitted in the design. The CPLD circuit is a method for centrally programming some logic relationships of the circuits on the board. Its function is to provide pulse signals and circuit logic required by the target board. Its functionality can be fully implemented using logic circuits and MPC823e pins. 4. System Hardware Startup and Reset The MPC823e reset methods include: power-on reset, external/internal hard reset, and external/internal soft reset. These methods are all handled by the reset controller. This system uses power-on reset, external hard reset, and external soft reset. This is completed internally by the chip. The MPC823e needs to acknowledge the PORESET signal, then samples the MODCK [1-2] pin signals. In the design, the MODCK [1-2] pins are connected to a high level through a pull-up resistor, generating a 5x frequency multiplier until all internal PLLs (Phase2 Locked Loop) are locked, activating the system clock. Finally, PORESET returns to a high level. After the MPC823e finishes its power-on reset state, it locks all internal PLLs. The PowerPC core continuously drives the HRESET and SRESET signals, and then samples system configuration information from the data bus. When HRESET is active, the core also declares the SRESET signal active. After completing all startup or reset processes, the MPC823e enters the normal system software initialization state and runs the upper-level program. During the sampling of hardware reset configuration word information from the data bus, the RSTCONF signal must be active low; if RSTCONF is high, the system uses the internal default value as the hardware reset configuration word. When PORESET is active, the core uses the default value 0x000000000 as the configuration word. The author's development board design uses the latter method, i.e., RSTCONF is high. 5. Storage System Design The memory manager in the MPC823e is responsible for controlling and managing both GPCM and UPMA(B) memory control mechanisms, providing flexible timing support and seamless connectivity for different memory types. GPCM provides a simple, low-level interface for memory resources and memory mapping that does not support burst mode. Therefore, GPCM-controlled memory slots are mainly used for system startup and data access that does not support burst mode. The external serial port chip ST16C552 also uses the GPCM control mechanism. UPM, on the other hand, supports burst mode and includes external bus address multiplexing, periodic timing, and the generation of programmable row and column address strobe signals for the DRAM device. Therefore, UPM is often used to support high-performance real-time memory. In the memory design of this system, four Intel E28F128J3A FLASH chips are used, with a system capacity of 4x16M. Four Intel MT48LC32M16A2TG SDRAM chips are used, with a system capacity of 128M. In this design, BANK0 is used for FLASH, corresponding to the CS0 chip select signal. The memory management mechanism is GPCM, and the data bus width is 8x4 bits. SDRAM uses two BANKs, employing CS1 and CS2 chip select signals (CS1 is shown in Figure 3). The memory management mechanism is UPMB, and the data bus width is 32 bits. FLASH is used to store the BSP (Board Support Package), real-time operating system, and user applications. Setting the BYTE# (Byte Enable) pin allows the Flash to operate in x8 or x16 mode. Timing control for SDRAM read/write and burst mode is implemented by programming the MPC823e GPL[0:3], with the clock provided by the MPC823e's CL KOU T signal. The MPC823e's byte strobe signals BS[0:3] are connected to the SDRAM's U(L)DQM pin to select the byte channel. Figure 3 is a schematic diagram of the memory hardware design. For other external memory on the user card that may exist, this system reserves several chip select signals. [align=center] Figure 3 Memory Hardware Design Diagram[/align] 6. Hardware Design of Various Communication Interfaces The MPC823e's communication processor module (CPM) provides a flexible and complete solution for various communication environments. To reduce system frequency and save power, the CPM has an independent RSSC communication processor (CP) to optimize various serial communications. The CP provides services for several integrated communication channels, performs low-level protocol processing, and controls DMA. The CPM reduces the computational tasks of the core through the following means: reducing interrupt generation rate; performing some OSI Layer 2 processing; and supporting multiple cache memory data structures. Based on the CPM's functions, the peripheral communication circuit only needs to provide physical layer transceivers and drivers. In this system design, the Ethernet transceiver uses Intel Level One's LXT905; the RS232 transceiver uses MAXIM's MAX3225ECAP; and the USB transceiver uses Philips' PDIUSBP11A. The Ethernet transceiver uses the MPC823e's SCC2; the RS232 transceiver uses the MPC823e's SMC1; and the USB transceiver uses the same USB interface as the MPC823e. Since the LXT905 itself provides a seamless interface with the MPC823e, communication with the outside world via RJ45 mainly focuses on protocol implementation and data transmission/reception control. Its data interface signals include: ● RCLK and TCLK: Receive and transmit clock signals. Provided by the LXT905 and connected to the MPC823e's clock signal CLKx. ● RXD and TXD: Receive and transmit data signals. Provided by the MPC823e and connected to the LXT905's RXD and TXD. ● TEN: Transmit enable signal, simultaneously starting the LXT905's watchdog timer. ● CD: Carrier listener signal, monitoring whether the LAN is in use. ● COL: Conflict monitoring signal, the conflict monitoring input of the drive controller. The external interface diagram of the multimedia system is shown in Figure 4: [align=center] Figure 4 External interface diagram of the multimedia system[/align] The description of the hardware debugging and testing part is omitted here. 7 Conclusion Based on the underlying design, the multimedia hardware development platform of MPC823e selects the corresponding embedded operating system, and then develops the relevant drivers and upper-level applications. It is connected to the respective development system through the required interface, and finally various communication and network products can be designed and implemented. References: [1] Zou Siyi, ed. Embedded Linux Design and Application. Tsinghua University Press, 2002 [2] Motorola Inc. MPC823e Integrated Communications Microprocessor User's Manual. Motorola Inc., 2000