Abstract: This paper introduces a high-reliability power distribution network monitoring system based on the combination of ADC and DSP processor. This system not only features a simple hardware design but also high reliability and fast measurement speed. Keywords: Power quality; FFT; Spectral leakage; Hedge fence effect; Harmonics Introduction Power quality is a standard for measuring power grid quality. Power quality problems include voltage sag, voltage swell, spikes, harmonic aberration, and electric yawp, among which harmonic aberration has the greatest impact on power quality. Therefore, the design of this system focuses on harmonic aberration analysis. There is considerable research in this area, and corresponding equipment has been developed. Previous power distribution network monitoring equipment mostly used 51 and 96 series microcontrollers as processors, which could not meet the requirements of power systems in terms of accuracy and speed. Another approach was to use TI's DSP as the processor, combined with an ADC, to complete the system design. Analog Devices (ADI) has successively launched dedicated power measurement chips such as the ADE7753 and ADE7758, and successfully applied them to the power grid. Recently, Analog Devices (ADI) launched a high-performance, powerful combination: a DSP + ADC power measurement solution. This monitoring system utilizes this combination. Figure 1 shows the system hardware design block diagram, and Figure 2 shows the software block diagram. ADC Introduction : The AD73360 is an IC from ADI specifically designed for power quality monitoring. Compared to general ADCs, the AD73360 offers the following advantages: six independent A/D conversion channels that not only do not interfere with each other but also strictly guarantee sampling synchronization; high precision, with six 16-bit conversion precision channels perfectly suited for power quality monitoring needs; and a programmable sampling rate within the range of 8kHz, 16kHz, and 32kHz, providing wide applicability. The AD73360 offers four different input methods—DC/AC, single-ended/differential—to adapt to different applications; and a serial interface for easy connection to DSP chips. Considering accuracy, speed, number of sampling channels, and synchronous sampling, the AD73360 is an ideal choice for power monitoring systems. DSP Introduction The system uses the ADSP2191M, a 16-bit fixed-point DSP from Analog Devices (ADI). The ADSP2191M processor's resources are summarized as follows: Accessible memory space of 16M words, divided into 256 pages, each page being 64K words. Page 0 is internal RAM, page 255 is internal ROM, and the remaining space is divided into four parts, selectable by ms0 to ms3. There are 256 pages of I/O memory, each page being 1K words, with the first 8 pages being internal I/O memory and the rest being external I/O memory. The processor has one host interface, three synchronous serial interfaces, two SPI interfaces, 16 programmable flag pins, one asynchronous serial interface, and three 32-bit timers. Connection to the AD73360 must use a serial bus; the ADSP2191M has three such synchronous serial ports. Hardware Circuit Design The hardware design of the entire system is based on the ADSP2191M and AD73360, supplemented by peripheral circuits. The block diagram of the hardware design is shown in Figure 1. As can be seen from Figure 1, the hardware design is very simple, without the most troublesome synchronous holding circuit and system memory expansion. This is because the AD73360 can achieve multi-channel synchronous conversion, eliminating the need for synchronous holding circuit design; the ADSP2191M has 64K of internal RAM, which meets the system design requirements. In the system hardware design, the sensor is used to convert the power grid parameter electrical signal into the ADC input signal, which is then sent to the AD73360 for synchronous sampling. The converted sampled data is transmitted to the DSP processor through the synchronous serial port for data processing, harmonic analysis, and other operations. Finally, the processor sends the analysis results to the LCD for display and to the PC for further processing via the serial port. Flash memory is used to store the system code. In the entire system design, Flash and LCD are basic system expansions, and asynchronous serial port is basic development. Here, only the connection between the DSP processor and the ADC is introduced. They must communicate via a serial interface. The ADSP2191M uses a 6-wire serial interface, while the AD73360 uses a 5-wire serial interface. The difference lies in the serial clock: the former has separate serial transmit and receive clocks, which are independent, while the latter combines them into one. Comparing the timing diagrams reveals that their timings are basically the same. However, to control the AD73360, the processor must also meet the following requirements: the serial port can be set to external clock mode; the serial word length can reach 16 bits; each word transmitted and received has a synchronization frame signal; for the processor, the receive synchronization frame signal is the input signal, and the transmit synchronization frame signal is the input signal; the frame synchronization signal is generated in the clock cycle preceding the high-order bit of the serial word, and the frame synchronization signal is active high. As a processor similar to the AD73360, the ADSP2191M can easily meet these requirements through configuration. Figure 3: Comparison of Hardware System Analysis and Theoretical Analysis System Software Design The system software design is relatively complex, consisting of several parts including A/D sampling control, LCD control, serial port transmission, data processing, and harmonic analysis algorithms. The overall software block diagram is shown in Figure 2. The harmonic analysis algorithm has the largest and most important code, as it is responsible for analyzing the power quality of the distribution network. The Flash driver code is used to drive the STM29w040; it is not used in system monitoring but rather for downloading program code. The system development code uses a combination of DSP assembly language and C language, primarily C language with assembly language as a supplement. Regarding the processing of the 219x_int_tab.asm file: Before introducing the overall system flow, let's first discuss the 219x_int_tab.asm file. When the main function exists in a C file, the 219x_int_tab.asm file is considered part of the project by default, and the project's interrupt vectors are initialized. When an interrupt occurs, the program pointer jumps to the corresponding location in the file and uses the ___lib_int_determiner function to find the entry point of the interrupt service routine. If the service routine entry point cannot be found, it will cause a program deadlock and prevent normal operation. Implementing interrupt functions in C language is relatively complex. To improve system development speed and reduce system program code, the interrupt vector table in 219x_int_tab.asm needs to be modified first during system development. The interrupt service routine entry point can be directly assigned to the interrupt vector table to complete the function's functionality. The system software development tool is VisualDSP++ 3.0. In software design, the most important aspect is the design of the harmonic analysis algorithm. This is because it is the core of the software design, not only involving a large amount of code but also being one of the decisive factors in the system's measurement accuracy. This scheme uses the mature FFT (Fast Fourier Transform) algorithm as the system's harmonic analysis algorithm. Simultaneously, to suppress the picket fence effect and spectral leakage problems inherent in the FFT algorithm, a Hanning window and interpolation algorithm are added. Due to the large amount of code, the source code is not provided here. The system software design uses two interrupts: synchronous serial port transmit interrupt and synchronous serial port receive interrupt. The former is used to configure the AD73360, and the latter is used to read the converted sampled data from the AD73360. Their code is also not detailed here. In addition, the system also features an asynchronous serial port, a programmable flag pin, and LCD control, making the entire system more intelligent and user-friendly. These will not be detailed here. Comparison of System Analysis and Software Analysis After system development was completed, a comparison with software analysis was used to evaluate the system analysis results. The raw time-domain data was imported into Matlab software, and the FFT algorithm within the software was used to analyze the data, yielding a set of corresponding time-domain waveforms, amplitude spectra, and phase spectra. Comparing these graphs with the corresponding graphs obtained from the system hardware analysis in the DSP system reveals the differences between the hardware system analysis and the theoretical analysis. Figure 3 shows the comparison of these graphs. The raw data analyzed by the DSP hardware system and the Matlab software are the same, but the analysis methods used are different: one is the algorithm developed by the system, and the other is a tool built into the software. Therefore, the reliability of the developed system's algorithm can be verified through comparison. It can be seen that in the comparison graph, the waveforms, amplitude, and phase spectra of the time-domain signals obtained by the developed system are quite consistent with the analysis results of the Matlab software. Due to space limitations, the final analysis data will not be detailed further. To compare the system's reliability, multiple analyses were conducted. The comparative data showed that although different analysis systems were used, the results were very similar with minimal error, indicating that the system's hardware monitoring results have considerable reliability. Conclusion Using the AD73360 and ADSP2191M processors as the system hardware core, the system has the following characteristics: • Simple hardware design, easy to implement and low cost. • No external SRAM expansion, resulting in low hardware requirements. • Utilization of unused DSP processor interface resources, facilitating system software upgrades. • The system software design employs a combination of assembly and C languages ​​and a windowed interpolation FFT algorithm, improving code development speed and overall measurement accuracy. The comparative results show that this scheme meets the requirements of power systems, has high reliability, and can at least meet the real-time sampling requirement of 160 points per cycle.