Abstract: This paper proposes a design scheme and implementation method for a high-precision data acquisition system composed of a high-speed, high-precision A/D conversion chip, a high-performance FPGA, a PCI bus interface, and a DB25 parallel interface. The FPGA serves as the control core and transmission bridge of the system, employing both parallel and PCI bus interface data transmission modes, allowing for convenient switching between the two modes. Finally, the FPGA is developed using Quartus II software, and upper-level control software for PC applications is written using VB. Keywords: Data acquisition; PCI; Parallel interface; FPGA 1 Introduction With the rapid development and popularization of computer technology, data acquisition systems have also been rapidly applied. In the production process, this system can be used to collect, monitor, and record process parameters on the production site, providing information and means to improve product quality and reduce costs. A typical data acquisition system consists of A/D + DSP + FPGA (CPLD) + D/A. This paper implements a high-precision data acquisition system that can be used in two interface (PCI and parallel interface) transmission modes using the AD6644 analog-to-digital converter chip and an FPGA. 2 Hardware Circuit Design 2.1 System Design Scheme This data acquisition system mainly consists of three parts: analog, digital, and interface, as shown in Figure 1. The analog part mainly includes an analog intermediate frequency signal preprocessing module and an analog-to-digital converter module; the digital part, except for the clock generation circuit, is entirely designed in the FPGA; the interface part includes a PCI bus interface, a DB25 parallel interface, and a SignalTapII logic analyzer debugging interface. The design concept of this system is as follows: First, the analog intermediate frequency signal preprocessing module inputs the adjusted analog signal to the A/D converter, and then, after analog-to-digital conversion, the 16-bit digital signal (AD6644 outputs 14 bits, plus 2 parity bits) is directly output to the FPGA for storage. A high-speed buffer DCFIFO and a high-speed memory DPRAM, along with a series of timing control logic, are designed in the FPGA to ensure real-time storage of data sent by the ADC within a predetermined capacity. Simultaneously, two data transmission interfaces are designed in the FPGA, allowing the system to transmit data in a selected mode, either through the parallel interface or the PCI bus interface. [align=center] Figure 1 System Overall Block Diagram[/align] 2.2 Analog Intermediate Frequency Signal Preprocessing Module First, the input signal is passed through a two-stage amplifier to ensure that the amplitude of the analog input signal meets the requirements of the AD6644 input amplitude and to provide good isolation for the analog input signal. Here, the AD9618 is selected to implement the amplification function of the analog signal. The AD9618 has high unity-gain bandwidth and slew rate, which can amplify the analog input signal and improve its performance. The circuit diagram is shown in Figure 2. [align=center] Figure 2 Schematic Diagram of Two-Stage AD9618 Amplifier[/align] Next, the amplified single-ended signal is converted into a differential signal by the AD8138 and then output to the AD6644. This is because, as a new type of high-switching-speed, large-dynamic-range ADC, the analog input signal of the AD6644 requires differential form to ensure its performance. Using differential input in the analog signal stage can effectively filter out even-order harmonic components, while also effectively suppressing other common-mode spurious signals (such as noise introduced by power supply and ground) and feedback signals from the crystal oscillator. As shown in Figure 3, the AD8138 is used to adjust the analog signal. The single-ended analog signal (AD9618_out) is converted by the AD8138 into differential analog signals (AIN, nAIN) with a gain of 1, and then sent to the AD6644 for analog-to-digital conversion. The DC bias voltage VREF of the AD8138 is provided by the precision reference source of the AD6644. Using differential input can improve the signal-to-noise ratio by approximately 3dB compared to single-ended input. 2.3 FPGA Configuration and Analog-to-Digital Conversion Module The FPGA part is the core module of this system, carrying all the digital circuitry. During the design process, the concept of SOC (System-on-Chip) is emphasized. All the digital logic required by the system is implemented on the FPGA platform, including flip-flops, memory, buffers, PLLs (Phase-Locked Loops), counters, decoders, multiplexers, DB25 interface logic, PCI interface logic, etc. This makes the digital part of the system fully programmable and adjustable, requiring only updates to the FPGA program as needed, offering strong adaptability and flexibility. Based on this approach, we selected Altera's Cyclone series FPGA—EP1C6Q240C8. [align=center] Figure 3 AD8138+AD6644 Connection Schematic[/align] In this system, two configuration methods were used: AS mode and JTAG mode. These two configuration methods can be used together, requiring only two sets of terminals on the board, with the ByteBlaster II download cable. First, the JTAG mode was used in conjunction with the SignalTap II in-circuit logic analyzer included in Quartus II to debug the FPGA's functions and timing. After successful debugging, the AS+EPCS4 mode was used to download the program to the configuration chip EPCS4, ensuring automatic program loading for the FPGA every time the system powers on. It should be noted that when using this configuration method, if JTAG and AS modes start loading simultaneously, JTAG mode will automatically gain priority and load the program, while AS mode will automatically terminate. The A/D converter chip used is the Analog Devices (ADI) AD6644. The AD6644 is a high-speed, high-performance 14-bit 65MSPS monolithic analog-to-digital converter (ADC) with integrated sample-and-hold circuitry and reference voltage circuitry, providing a complete conversion application solution. The AD6644 is a representative chip in ADI's Softcell receiver chipset, specifically designed for third-generation mobile communication systems, and is particularly suitable for multi-channel, multi-mode receiver applications. Compared to other chips, the AD6644's spurious-free dynamic range exceeds 100dB in the Nyquist frequency range, significantly enhancing its ability to detect useful small signals from input spurious components, making it more suitable for multi-mode digital receivers. Simultaneously, the AD6644's typical signal-to-noise ratio reaches 74dB. The AD6644 can also be used in single-channel digital receivers, such as wide-channel bandwidth systems, accurately converting wideband analog signals (200MHz input bandwidth). Through undersampling, harmonic components can be distributed outside the useful frequency band, and when used in conjunction with a digital down-converter chip, the noise plateau within the useful signal bandwidth can be reduced. 2.4 Clock Generation Module [align=center] Figure 4 Working Principle Diagram of Dual-Mode Prescaler MC12013 [/align] The clock of this acquisition system is generated by an external crystal oscillator or clock signal generator, then prescaled and applied to the dedicated clock pin input of the FPGA, using the global clock network in the FPGA for routing. We use the dual-mode prescaler MC12013 for prescaler division. The MC12013 is an ultra-high-speed dual-mode prescaler with bipolar emitter-coupled transistor logic. The modulus ratio is 10/11, and the division ratio is determined by the high or low level of the mode control. The MC12013 is an ECL integrated circuit with a maximum operating frequency of 550MHz and an internal ECL-to-TTL conversion circuit. When the modulus control output is high "1", the dual-mode prescaler operates at the low-mode division ratio M; when it outputs low "0", it operates at the high-mode division ratio M+1. This system only uses the divide-by-10 function, and its working principle is shown in Figure 4. 2.5 Interface Design This system uses two interface methods: the DB25 parallel interface and the PCI bus interface. Although both interfaces transmit data acquired by the analog-to-digital converter module and stored in the FPGA to the PC, their operating processes are different. When using the DB25 parallel interface for data transmission, due to the limitation of the parallel interface's transmission rate (only about 1MBps in EPP mode), when the A/D converter performs high-speed sampling (such as AD6644 operating at 50MHz), the parallel interface cannot completely read the data stored in the FPGA by the ADC in the same amount of time. Therefore, real-time transmission cannot be achieved at this time; the system must operate in a store-and-forward state. That is, when the acquired data in the ADC fills the RAM memory in the FPGA, the data acquisition work stops, and the data reading process resumes. After the DB25 completely transmits the data in the FPGA memory to the PC, the ADC data acquisition process restarts, and this process repeats until all data acquisition, storage, and forwarding are completed. When using the PCI bus interface to transmit data, due to the high transmission rate of the PCI interface (33MHz*32bit transmission mode is used in this system), even when the A/D converter is performing high-speed sampling, the PCI interface is still capable of reading the data stored in the FPGA by the ADC into the PC within the same time. Therefore, real-time data acquisition and storage can be achieved to a certain extent. 3 FPGA and PC-side control software design The biggest difference between Altera's FPGA products and those of other companies is that it adopts a continuous interconnect structure, that is, it uses a series of metal lines of the same length to interconnect logic units. The continuous interconnect structure eliminates the difference in transmission delay in the segmented interconnect structure of FPGA, providing a fast path with a fixed delay between logic units. The advantage of this structure is that the routing speed is fast and it is easy to simulate, which can shorten the development cycle when implementing complex and large-scale designs. There are two software programs for developing Altera's programmable logic devices: Quartus II and MAX+PLUS II. This design uses Quartus II development software, which provides a fully integrated design environment that is independent of the structure, allowing designers to easily input design data, process it quickly, and program devices for various Altera product families. The Quartus II development system boasts powerful processing capabilities and high flexibility. In this system, the FPGA acts as a control and transmission bridge, using control and transmission signals from the PC host to systematically control the ADC sampling, data storage, and transmission processes. The tasks of determining the system's start-up time, the interface transmission mode, data storage on the PC, and displaying the original waveforms from the acquired data are all handled by the control software installed on the PC. We implemented this control software using a VB program. In the Windows environment, the data acquisition system acts as an external device, and we will use the dynamic link library (TVicHW32.DLL) to perform read and write operations. TVicHW32.DLL can directly control and read/write memory, I/O ports, interrupts, etc., and we will use some of its functions here. The author's innovation: The scheme designed in this paper uses the FPGA as the control core and transmission bridge of the entire data acquisition system. On the one hand, it can perform precise timing control of the entire system's operating mode and state according to the instructions from the host computer; on the other hand, it can utilize the rich macro function block resources and embeddable IP core resources of the FPGA to implement high-speed caching and high-speed data transmission interfaces. References: [1] Zhang Ruixiang, Zhao Junhong. Fault detection system for asynchronous motor based on data acquisition card [J]. Ordnance Automation, 2006 [2] Xu Haijun, Ye Weidong. Application of FPGA in high-performance data acquisition system [J]. Measurement Technology, 2005 [3] Qiushi Technology. CPLD/FPGA Application Development Technology and Engineering Practice [M]. Beijing: Posts & Telecom Press, 2005 [4] Zhao Hongmei, Mi Qichao. Design of multi-channel data acquisition system based on DSP and FPGA [J]. Microcomputer Information, 2007, 9-2: 197-198