[b]1 Introduction[/b] In the variable frequency home appliance industry, AC-DC-AC frequency converters are increasingly widely used. The front stage of such frequency converters generally uses uncontrolled rectifier bridges and electrolytic capacitor filters, which generate serious harmonic current pollution on the grid side, causing the products to fail IEC61000-3-2 and IEC61000-3-12[sup][1-2][/sup]. Therefore, it is necessary to install an active power factor corrector in the front stage of these devices. The traditional active power factor corrector is a fully active PFC. Although the correction effect is good, the power device loss is large and the heat generation is also serious under high power conditions. The partial PFC circuit proposed in reference [3] is actually a buck type PFC circuit. Although the correction effect and efficiency are very good, the DC side voltage drops significantly under high power conditions because the electrical angle of the chopping interval is not adjustable, which reduces the modulation of the downstream inverter system and reduces the constant torque range of the motor. In addition, the PFC circuit adopts a modulation scheme with a fixed switching frequency in the chopping interval, which makes the system generate a strong EMI near the switching frequency. If a modulation strategy with a changing switching frequency is adopted, the EMI near the switching frequency will be greatly reduced. In view of the above points, this paper studies a new type of partially active PFC circuit based on the high-efficiency circuit topology of bridgeless PFC and adopts a switching frequency modulation method. The DC bus voltage is adjusted by adjusting the electrical angle of the chopping interval, which belongs to a buck-boost type converter. The essence of the bridgeless PFC circuit is revealed through theoretical analysis, and simulation analysis and experimental research are carried out. 2 Principle analysis of partially PFC circuit [b] 2.1 Traditional partially PFC circuit [/b] The partially PFC circuit proposed in reference [3] is based on the traditional single-phase boost topology as shown in Figure 1, and adopts a double-ended pulse control scheme with a fixed electrical angle chopping as shown in Figure 2. [img=227,147]http://www.ca800.com/uploadfile/maga/inv2008-8/2-1.jpg[/img]Figure 1 Traditional single-phase PFC circuit topology[img=283,153]http://www.ca800.com/uploadfile/maga/inv2008-8/2-2.jpg[/img] [align=center]Figure 2 Fixed electrical angle dual-ended pulse control scheme[/align] The traditional single-phase PFC circuit shown in Figure 1 uses a total of six power devices. At any given moment, three power devices are in operation. This has disadvantages such as high losses and high cost. In addition, the circuit is asymmetrical, so the EMI is also strong. Figure 2 shows a partial PFC circuit using a fixed electrical angle dual-ended pulse control scheme. During the positive/negative cycles of the input power supply, in the lower voltage range (0-θ_sub1 and θ_sub-π), the power switch S is controlled. In the range near the peak voltage (θ_sub1-θ_sub2), the power switch S is always off. Typically, θ_sub1 is π/3 and θ_sub2 is 2π/3. Using this dual-ended pulse control scheme with a fixed chopper electrical angle, the DC bus voltage drops significantly under high power output conditions, reducing the constant torque range of the motor downstream of the inverter. Therefore, traditional partial PFC circuits have low efficiency and are only suitable for medium- and high-power applications where DC bus voltage requirements are not high. [b]2.2 Novel Bridgeless Partial PFC Circuit[/b] Based on the two shortcomings of traditional partial PFC circuits, this paper adopts a high-efficiency bridgeless PFC topology (Figure 3) and a variable electrical angle dual-ended pulse control scheme (Figure 4) to design an improved partial PFC circuit. The bridgeless PFC topology shown in Figure 3 [sup][4-5][/sup] has a simple circuit structure, using only four power devices. At any given moment, only two power devices are in operation. Compared with the traditional single-phase PFC circuit shown in Figure 1, it reduces the loss of one power device under the same operating conditions, resulting in lower losses and higher efficiency. Furthermore, the circuit is completely symmetrical, which also helps reduce the system's EMI. [img=340,202]http://www.ca800.com/uploadfile/maga/inv2008-8/2-3.jpg[/img]Figure 3 Circuit topology of a single-phase bridgeless PFC[img=283,160]http://www.ca800.com/uploadfile/maga/inv2008-8/2-4.jpg[/img]Figure 4 Improved variable electrical angle double-ended pulse control scheme Figure 4 shows the variable electrical angle double-ended pulse control scheme adopted in this design. Unlike the traditional fixed electrical angle double-ended pulse control scheme shown in Figure 2, during the positive/negative half-cycle of the power supply voltage, from 0 to θ1, the power supply voltage is very low. Even with a duty cycle close to 100%, the current rise is very slow during this time. Therefore, the power switch is not controlled to chop the input current during this period. Similarly, from θ4 to π, the power supply voltage is not chopped; instead, the inductor's freewheeling effect is used to allow the input current to naturally decrease to zero. During the power supply voltage periods of θ1 to θ2 and θ3 to θ4, the power switch is controlled to operate, putting the circuit in a forced rectification state. During the period of θ2 to θ3, when the power supply voltage is higher, the power switch is stopped, allowing the circuit to operate in a natural rectification state. The timing of θ2 and θ3 is determined by the load power. The larger the load, the larger the active PFC duration θ2. Generally, the electrical angles θ2 and θ3 are complementary. Using the above pulse control scheme, the DC bus voltage can be easily adjusted by adjusting the electrical angle θ2 according to the load size. Theoretically, θ2 can vary from 0 to π/2. In practical applications, to obtain a better current correction effect, θ2 is generally taken as π/3 to π/2. When θ2 is small, the obtained DC bus voltage will be lower than the peak value of the input AC voltage, and the circuit belongs to the buck type. When θ2 is π/2, the circuit operates in the same way as the full PFC state, and the DC bus voltage will be much higher than the peak value of the input AC voltage, which belongs to the boost type. Therefore, this improved partial PFC circuit belongs to a buck-boost type PFC circuit. [b]2.3 Implementation of Reducing System EMI Using Switching Frequency Modulation[/b] Traditional PFC circuits generally use a modulation method with a constant switching frequency in the chopping range, resulting in strong EMI near the switching frequency and its integer multiples. Using switching frequency modulation can significantly reduce the system's EMI. Some PFCs inherently include a special switching frequency modulation method, and the use of an MCU further facilitates the implementation of switching frequency modulation. [img=340,196]http://www.ca800.com/uploadfile/maga/inv2008-8/2-5.jpg[/img] Figure 5 Modulation Law of Switching Frequency The solid line in Figure 5 shows the variation law of the switching frequency over half a power supply cycle. During the forced rectification periods θ1～θ2 and θ3～θ4, the switching frequency varies along an inverted sine curve, with a maximum variation range of 9kHz～10kHz and a modulation depth of approximately 10%, which is considered optimal. The switching frequency is lowest when the power supply voltage is highest and highest when the power supply voltage is lowest. During the natural rectification phases from 0 to θ1, θ2～θ3, and θ4～π, the switching frequency becomes zero. Using a switching frequency modulation method that varies according to the above pattern allows the high-frequency conducted EMI on the power supply side to be dispersed over a wider frequency spectrum, which helps reduce the system's average EMI and quasi-peak EMI, compensates for the strong common-mode conducted interference of bridgeless PFCs, and simplifies the design of the input EMI filter. 2.4 The Essence of BLPFC Regardless of whether it is a passive or active PFC circuit, when the power factor correction effect is satisfactory, the voltage of the DC electrolytic capacitor must be a DC component superimposed with an AC ripple voltage with a frequency of 2ω1 and a phase lag of π/2 behind the power supply voltage, where ω1 is the angular frequency of the power supply. From the single-phase bridgeless PFC circuit shown in Figure 3 and the two-terminal pulse control scheme in Figure 4, it can be seen that to obtain the DC voltage on the electrolytic capacitor, during the positive half-cycle of the power supply, the envelope of the bridge voltage νab should be consistent with the waveform of the ripple voltage on the electrolytic capacitor; during the negative half-cycle of the power supply, the envelope of νab should be symmetrical about the horizontal axis to the envelope of the ripple voltage on the electrolytic capacitor, as shown in Figure 6. [img=340,268]http://www.ca800.com/uploadfile/maga/inv2008-8/2-6.jpg[/img] Figure 6 shows a schematic diagram of the voltage waveform before the BLPFC bridge. Curve 1 in Figure 6 represents the waveform of the voltage νab before the bridge, and curve 2 represents the DC ripple voltage waveform on the electrolytic capacitor. The amplitudes of the two curves differ by the forward voltage drop of two rectifier diodes. During the time intervals θ1～θ2 and θ3～θ4, the voltage νab before the bridge is in a discontinuous pulse form because the power switch is in a chopping state. However, the envelope of the pulse is consistent with the waveform of the voltage on the electrolytic capacitor. The frequency of the voltage νab before the bridge shown in Figure 10 is ω1, which, in form, contains a harmonic component with a frequency of 2ω1. However, due to the strict symmetry in structure and control of the bridgeless PFC circuit shown in Figure 3, the even-order harmonic current content is greatly reduced, and the circuit should only contain odd-order harmonic current components. Given that the bridge-before voltage waveform shown in Figure 6 is similar to the bridge-before voltage waveform of a passive PFC using harmonic reactors or similar series connections, the bridgeless PFC circuit exhibits the characteristics of general series compensation to improve the power factor, and thus belongs to a series compensation scheme. Traditional active full PFCs also exhibit the characteristics of general series compensation to improve the power factor, manifested in the voltage waveform of the fast recovery diode rectifier anode to DC ground having a voltage pattern similar to the bridge-before voltage ν[sub]ab[/sub] of the bridgeless PFC, as shown in Figure 7. In Figure 7, curve 1 is the waveform of the bridge-before voltage ν[sub]ab[/sub], and curve 2 is the DC ripple voltage waveform on the electrolytic capacitor; the amplitudes of the two differ by the forward voltage drop of the FRD diode. [img=340,230]http://www.ca800.com/uploadfile/maga/inv2008-8/2-7.jpg[/img] Figure 7 Schematic diagram of voltage waveform of anode to ground in traditional PFC FRD 3 Simulation and analysis of bridgeless PFC circuit [b]3.1 Establishment of simulation platform[/b] The simulation circuit of part of active PFC established using Simulink simulation software is shown in Figure 8. The power circuit is the same as the bridgeless PFC topology shown in Figure 3. L1 and L2 are two common core inductors with the same inductance and wound in differential mode. The total inductance is 5.5mH. R2 is a constant power load with a power of 3.5kW (the output power can be arbitrarily designed). The input AC power supply voltage is 220V/50Hz, and the output capacitor E1 is 1880μF. The control circuit, following the pulse transmission pattern shown in Figure 4, controls power switches S1 and S2 to chop the input voltage during θ1～θ2 and θ3～θ4. The duty cycle is adjusted by comparing appropriate inverted sine and triangular waves. During the time interval θ2～θ3, S1 and S2 are turned off to put the circuit into a natural rectification state; the specific circuit details are not provided below. The simulation results for θ2 being π/3 and 5π/12 are compared below, demonstrating that increasing θ2 increases the average value of the DC loop voltage. [img=340,215]http://www.ca800.com/uploadfile/maga/inv2008-8/2-8.jpg[/img] Figure 8. Simulation circuit of active PFC without bridge. [b]3.2 Input current and output DC voltage waveforms under different conditions[/b] The input current waveforms for θ[sub]2[/sub]=π/3 and θ[sub]2[/sub]=5π/12 are shown in Figure 9, and the DC output voltage waveforms are shown in Figure 10. As can be seen from Figure 9, when θ[sub]1[/sub] increases from π/3 to 5π/12, the waveform of the input current becomes significantly smoother, and the waveform distortion is reduced, which is beneficial to further improve the power factor on the grid side. As can be seen from Figure 10, when θ[sub]2[/sub] increases from π/3 to 5π/12, the output voltage increases by about 15V. In home appliance applications such as inverter air conditioners, there is a problem where increased load leads to a decrease in output voltage, thus affecting the constant torque range of the motor. In a bridgeless active PFC circuit, the output voltage can be easily increased by appropriately adjusting θ[sub]2[/sub], thereby improving the constant torque range of the motor and conveniently solving this problem. [img=340,193]http://www.ca800.com/uploadfile/maga/inv2008-8/2-9.jpg[/img] Figure 9 Input current and input voltage waveforms (θ[sub]2[/sub]=π/3, θ[sub]2[/sub]=5π/12) [img=340,195]http://www.ca800.com/uploadfile/maga/inv2008-8/2-10.jpg[/img] Figure 10 Output DC voltage waveforms (θ[sub]2[/sub]=π/3, θ[sub]2[/sub]=5π/12) Theoretically, as θ2 increases, the expected average DC output voltage is higher, and the maximum value should be the peak value of the grid voltage. To verify this understanding, we set θ_sub = π/2, keeping all simulation conditions unchanged, and set the output DC voltage to 318V. At this point, natural rectification only occurs in the neighborhood where the maximum input current is very small. The average DC voltage is 308.3V, and the peak-to-peak DC voltage ripple is 20.0V. The input current and voltage waveforms are shown in Figure 11, and the DC voltage ripple waveform is shown in Figure 12. This indicates that a short-time critical natural rectification process will only occur when the output voltage is slightly higher than the peak input voltage by an increment. The increment above the input voltage amplitude belongs to the line's natural rectification. [img=340,182]http://www.ca800.com/uploadfile/maga/inv2008-8/2-11.jpg[/img] Figure 11 Input current and input voltage waveforms (θ[sub]2[/sub]=π/2) [img=227,125]http://www.ca800.com/uploadfile/maga/inv2008-8/2-12.jpg[/img] Figure 12 Output DC voltage ripple waveform (θ[sub]2[/sub]=π/2) [b]3.3 Comparison of electrolytic capacitor ripple voltage and bridge voltage waveforms[/b] When θ[sub]2[/sub]=5π/12, the waveforms of the electrolytic capacitor DC ripple voltage and bridge voltage are shown in Figure 13. As shown in Figure 13, the frequency of the DC ripple voltage on the electrolytic capacitor is 2ω1, which is twice the frequency of the power supply voltage, lagging behind by π/2. The waveform of the bridge-front voltage uab is a discontinuous pulse during the forced rectification stage, and a continuous waveform during the natural rectification stage. The envelope of the entire waveform is consistent with the waveform of the DC ripple voltage on the electrolytic capacitor, with a difference in amplitude equivalent to the voltage drop of two diodes. The frequency of uab is ω1, and its trend follows the power supply voltage. [img=227,139]http://www.ca800.com/uploadfile/maga/inv2008-8/2-13.jpg[/img] Figure 13 Comparison of electrolytic capacitor ripple voltage and bridge-front voltage (θ1=5π/12) Fourier analysis was performed on the bridge-front voltage waveform shown in Figure 13, and the results are shown in Figure 14. As shown in Figure 14, the bridge voltage uab mainly consists of the fundamental frequency and odd harmonic voltages, while the even harmonic components are negligible. The fundamental frequency voltage primarily forms the DC component of the electrolytic capacitor voltage and the 2ω1 ripple voltage. Other odd harmonic voltages contribute less to the DC component and generate higher-order ripple voltages that double the frequency. The resulting DC loop voltage fft waveform is shown in Figure 15. [img=227,148]http://www.ca800.com/uploadfile/maga/inv2008-8/2-14.jpg[/img] Figure 14 FFT analysis of the voltage before the bridge [img=283,183]http://www.ca800.com/uploadfile/maga/inv2008-8/2-15.jpg[/img] Figure 15 FFT analysis of the DC loop voltage 4 Experiment and analysis of the bridgeless PFC circuit [b] 4.1 Establishment of circuit topology[/b] Based on the above theoretical analysis and simulation results, a partially active PFC circuit based on the bridgeless topology was designed, as shown in Figure 16. This circuit includes a power circuit and a control circuit. The power circuit consists of filter inductors L1 and L2, a bridgeless PFC intelligent module (as shown by the dashed line in Figure 20), filter capacitors C1 and C2, and an electrolytic capacitor group E1. Compared with the traditional active PFC circuit, the number of components used in the circuit is greatly reduced. [img=340,162]http://www.ca800.com/uploadfile/maga/inv2008-8/2-16.jpg[/img] Figure 16 Experimental circuit design of the bridgeless PFC. The rated output power of the circuit is 3.5kW, and the controller uses ST's 8-bit microcontroller ST7MC1K2 with a main frequency of 16MHz. The AC mains input voltage range is 150V～265V; the efficiency is at least 90% when the mains voltage is at its lowest; the power factor is not lower than 0.95; in order to reduce the EMI intensity of the system, a switching frequency modulation scheme is adopted, so that the switching frequency varies between 9kHz and 10kHz, which is achieved by changing the PWM timing time of the microcontroller. The capacitor value is 1410μF (using three 470μF/400V electrolytic capacitors in parallel), and the total inductance is 5.5MH. According to the output power of the circuit, the bridgeless PFC intelligent power module FPAB50PH60 produced by Fairchild Semiconductor is selected. [b]4.2 Implementation of Switching Frequency Modulation[/b] The switching frequency changes according to the pattern shown in Figure 4. Considering the good linearity of the sine function in the time intervals θ1～θ2 and θ3～θ4, a linear function is used to approximate this segment of the sine function in the experiment, and this is implemented through microcontroller software programming. Based on the relationship between the output voltage and input voltage of a traditional active PFC circuit, the relationship between the output voltage and input voltage of a partial active PFC during the forced rectification stage is obtained as udc/│vin(t)│1/(1-d), where d is the duty cycle of the driving pulse. The variation law of the driving pulse duty cycle can be obtained as d=1-│vin(t)│/ udc. In actual operation, the calculated d should be appropriately adjusted according to factors such as load weight and electrolytic capacitor capacity to ensure that the sinusoidal nature of the input current is high and the harmonic content meets relevant standards. [b]4.3 Experimental Results and Analysis[/b] Within the output power range from light load to heavy load 3.5kW, the experimental conditions corresponding to θ_sub = π/3 and θ_sub = 5π/12 were tested respectively. The results show that, since sin(5π/12) - sin(π/3) ≈ 0.1, the average potential output DC voltage in the case of θ_sub = 5π/12 is about 1/10 of the amplitude of the grid voltage in the former case, approximately 31V. However, since there are infinitely many PWM pulse solutions that meet the IEC 61000-3-2 standard, a lower θ₁ can also obtain a higher output DC voltage, which is also related to the capacitance of the electrolytic capacitor and the load weight. One set of experimental conditions was: input voltage 220V, resistive load 50Ω. When θ₁ = π/3, the measured input active power is 1.72 kW, the power factor is 0.99, the total effective value of the input current is 7.68 A, the output voltage is 288 V, and the maximum peak-to-peak value of the ripple voltage is 13.9 V. The corresponding test waveform is shown in Figure 17. When θ₁ = 5π/12, the measured input active power is 1.80 kW, the power factor is 0.99, the total effective value of the input current is 8.15 A, the output voltage is 298 V, and the maximum peak-to-peak value of the ripple voltage is 19.9 V. The corresponding test waveform is shown in Figure 18. [img=227,178]http://www.ca800.com/uploadfile/maga/inv2008-8/2-17.jpg[/img] Figure 17 Input voltage and current waveforms when θ[sub]1[/sub]=π/3 [img=227,170]http://www.ca800.com/uploadfile/maga/inv2008-8/2-18.jpg[/img] Figure 18 Input voltage and current waveforms when θ[sub]1[/sub]=5π/12 Comparing Figures 17 and 18, it can be seen that when θ[sub]1[/sub] increases from π/3 to 5π/12, the input current becomes significantly smoother, the sinusoidal degree increases, and the output voltage also increases by about 10V, thus verifying the results of the above analysis. The experimental results show that, throughout the entire power range, the partial PFC using the bridgeless topology can achieve good correction effects and a high power factor. Furthermore, by adjusting the active PFC's operating time (specifically by adjusting θ[sub]2[/sub]), the output DC voltage can be easily adjusted. To adapt to different national power grid standards, a partial PFC was designed to operate at a power grid frequency of 60Hz. The hardware circuit remained unchanged; due to the frequency change, the output signal of some circuits, such as the current detection circuit, needed adjustment, requiring modification of the PWM mode. The control circuit remained unchanged, and very satisfactory experimental results were still achieved. 5. Conclusion This paper proposes a bridgeless partial active PFC circuit with adjustable chopper angle. By adjusting the chopper angle, the DC-side output voltage can be easily adjusted, making it a buck-boost type PFC circuit. This solves the problem of severe DC-side voltage drop leading to a narrower constant torque range in existing partial PFC schemes under high power conditions. Simultaneously, a switching frequency modulation scheme was adopted to reduce the EMI near the switching frequency and its integer multiples. After theoretical analysis, simulation analysis, and experimental testing, it is possible to ensure that the harmonic currents on the AC input side meet the IEC 61000-3-2 standard under various loads, the input power factor reaches 0.99 under medium load, the average output DC voltage is close to the grid voltage amplitude under light load, and the average output DC voltage is not lower than the grid voltage amplitude by 40V under heavy load. This can improve the modulation of the downstream inverter and improve the speed regulation characteristics of the motor. This scheme is particularly suitable for PFC applications with buck output voltage requirements, high power, and high EMI requirements, especially for high-power PFC applications, and has a promising application prospect. [b]About the Author[/b] Wang Han (1982-) Male, currently a doctoral student in the Department of Electrical Engineering, Shanghai Jiao Tong University, specializing in power electronics and electric drives. [b]References[/b][1] IEC 61000-3-2: 1995 “electromagnetic compatibility part3: limits-set.2: limits for harmonic current emission (equipment input current≤16a per phase)” [2] Daniel M. Mitchell. AC-DC converter having an improved power factor”, patent no. US 4,412,277. Rockwell Corp, 1983 [3] Yang Xinghua. Analysis and implementation of a novel part-active power factor correction circuit. Electrical Applications, 2007, 26(7): 54-57 [4] Lu B, Brown R, Soldano M. Bridgeless PFC implementation using one cycle control technique. Twentieth Annual IEEE APEC, 2005 [5] Srinivasan R, Oruganti R. A unity power factor converter using half-bridge boost topology. IEEE Transactions on Power Electronics [6] Fairchild. fpab30ph60 datasheet, jan, 2006