Abstract: For microcomputer-embedded application systems, system reliability is paramount; only high reliability can guarantee normal system operation. In industrial settings, due to harsh working environments and numerous interference sources, the reliability requirements for intelligent instruments that need to continuously record data are even higher. This paper takes the anti-interference design of a smart energy meter as an example. Based on the characteristics of the energy meter's working environment, it analyzes the factors affecting the energy meter's reliability and proposes corresponding anti-interference measures for power supply system interference, which is the most serious factor affecting its reliability. I. Introduction For microcomputer-embedded application systems, system reliability is paramount; only high reliability can guarantee normal system operation. In industrial settings, due to harsh working environments and numerous interference sources, the reliability requirements for intelligent instruments that need to continuously record data are even higher. These instruments are characterized by: the ability to select the measurement range according to user requirements; data protection recording during power failure, including user-set range parameters and accumulated data results; and the ability to accurately read the saved data and continue accumulating data when the system is powered on and resumes operation. However, during power-on or power-off phases, the system's operating state is often unstable, easily leading to data read/write errors. Therefore, anti-interference and fault-tolerant measures need to be implemented in both hardware and software design. This paper takes the anti-interference design of a smart energy meter as an example. Based on the characteristics of the energy meter's operating environment, it analyzes the factors affecting the meter's reliability and proposes corresponding anti-interference measures for power supply system interference, which is the most serious factor affecting its reliability. II. System Functional Circuit Diagram Figure 1 shows the functional circuit diagram of the system relevant to the content of this paper. Its function is to protect the recorded data when the system is powered off and restore the recorded data when the system is powered on. [align=center][img=425,587]http://www.e-works.net.cn/images/127915295847031250.GIF[/img] Figure 1 System Functional Diagram[/align] The circuit includes an AT89C52 microcontroller, a MAX813 watchdog chip, an AT24C02 E2PROM memory chip, a voltage comparator A composed of an LM393 chip, and two inverters composed of 74HC04 chips. The two inverters are used to achieve voltage matching to ensure that the external interrupt signal voltage is between 0 and 5V. The voltage comparator issues an external interrupt signal when the system loses power, ensuring that the data recorded in the microcontroller's internal RAM is saved to the AT24C02 power-down protection chip before the system stops working. The diagram uses only one AT24C02 chip, so the chip select pins A0, A1, and A2 are grounded. WP is the write-protect input; when high, it provides write protection, and when low, normal read and write operations are possible. SCL is the serial clock input, and SDL is the serial data input/output. The AT24C02 is a serial E2PROM manufactured by Atmel with an I2C bus interface. The AT24C02's self-timed write cycle, including automatic erase time, does not exceed 10ms, with a typical time of 5ms. It typically has over 100,000 write cycles, and the effective data retention time is generally up to 100 years. It uses a single 5V power supply. III. Interference Factors Affecting Normal System Operation For microcomputer application systems, various interferences can occur in the working environment. These can be categorized into three main channels: spatial interference (e.g., electromagnetic radiation); power supply system interference (e.g., undervoltage or overvoltage in the power grid); and process channel interference (e.g., interference in measurement channels). Power supply system interference is the most severe. Most microcomputer embedded systems use DC power supplied by rectified, regulated, and filtered mains power. However, the mains voltage is not a pure sine wave, and its pollution level cannot be ignored. In industrial and mining enterprises, power grid pollution mainly originates from the switching of electrical equipment, fault tripping, and short circuits to ground. Monitoring of the power grid in a machinery manufacturing plant workshop showed that undervoltage occurred on average every 2-3 hours, with a maximum undervoltage of approximately 40 volts and a maximum duration of 2 seconds, averaging 0.3 seconds. Overvoltage occurred on average every 5-6 hours, with a maximum overvoltage of 17 volts and a maximum overvoltage duration of 0.8 seconds, averaging 0.2 seconds. In addition to interference from the power grid, the power supply circuit itself is also a source of interference, such as ripple and self-oscillation generated by the power supply circuit itself, and spike pulse noise generated by the switching power supply. Studies have shown that excessive surges and sags can also affect the normal operation of the system. If there are several consecutive surges or sags of ±10% or ±15%, the resulting oscillations can produce power supply voltage changes of ±30% to ±40%, making the system unable to operate normally. The main causes of system data recording errors are power grid voltage fluctuations during the system power-on and system operation phases, i.e., interference generated by the power supply system. Therefore, this paper adopts corresponding anti-interference measures in both system hardware and software to address the interference generated by the power supply system. In addition, for systems with extremely high requirements for the accuracy of recorded data, in order to ensure the accuracy and reliability of recorded data and prevent data errors caused by the system reading and writing data and data recording errors caused by damage to some storage units of the memory, it is also necessary to improve the fault tolerance of the system by using multiple recording methods, i.e., data backup redundancy. IV. System Hardware Anti-interference Measures For systems with power-down protection recording functions, it is necessary to improve the power supply quality of the power supply system, such as using various voltage stabilizers, power regulators, and other measures to eliminate the influence of power grid noise. To address the slow rise of supply voltage caused by inductance on the printed circuit board, decoupling capacitors can be added to the integrated circuits on the PCB. The capacitor value is typically 0.01μF to 0.1μF. To effectively eliminate the impact of false interruptions caused by power supply voltage fluctuations, corresponding measures must be taken in the system hardware circuitry to resolve the false switching of voltage comparator A caused by mains voltage fluctuations. Therefore, the voltage comparator circuit in this system adopts a Schmitt trigger circuit structure. The Schmitt trigger circuit is characterized by strong anti-interference capability, effectively eliminating the influence of various noises and voltage fluctuations in the circuit, preventing the comparator output waveform from unnecessarily switching due to various interferences. This reduces false interruption signals caused by interference, ensuring the normal operation of the entire system, and also reducing the number of false erase/write cycles of the AT24C02, thereby extending the lifespan of the AT24C02 and improving the overall system reliability. V. System Software Anti-interference Measures Although certain measures have been taken in the hardware to address voltage fluctuation interference, software methods are still needed to overcome the issues of CPU and memory operating state matching, external false interruption interference generated during system power-on, and false interruptions caused by voltage fluctuations during system operation. The software's anti-interference measures mainly target two types of interference: one is the potential data read/write errors caused by system incoordination during system power-on; the other is the false interruption caused by power supply voltage fluctuations during system operation, resulting in unnecessary write operations to the AT24C02. For intelligent cumulative recording instruments, at the start of operation, it is necessary to read the previous recording results, as well as some range and conversion ratio parameters set by the user. During system power-on, there are two types of interference that can cause data read/write errors. 1. Overcoming interference from slow power supply rise: Due to the inductance of the printed lines on the PCB board, the power supply voltage rises slowly. When the CPU is already working normally, the voltage comparison circuit output is still at a low level, issuing an external interrupt signal. Although the AT24C02 has a write protection terminal, due to system instability, without necessary software processing measures, the system will still generate an interrupt response, mistakenly modifying the recording results, i.e., writing the random numbers in the CPU's RAM into the AT24C02 during the power-on phase. Therefore, the CPU must be made to wait in software. Only when the comparator circuit outputs a high level is the CPU allowed to read data from the external memory, and only then can interrupts be enabled. 2. Overcoming interference from mismatched operating states of various parts of the system: During system power-up, there is still a matching problem between the operating states of the CPU and the memory. That is, before reading data, it is necessary to determine whether the external memory is working properly. Therefore, it is necessary to test the operating state of the AT24C02, that is, to send a feature word into the memory, then read it out, and determine whether the result is the same as the sent feature data. If they are the same, it proves that the external memory is working properly; otherwise, wait 10ms, then send the feature word again, until the read result is the same as the written data. The feature word can be 55H (01010101B) or AAH (10101010B). However, since the AT24C02 has a limited number of erase/write cycles, to prevent potential malicious situations, if the test is still incorrect after 3 attempts, the CPU enters an infinite loop. During this loop, the watchdog timer is not accessed. After a certain period (approximately 1.6 seconds, the maximum allowed access interval for the watchdog timer), the watchdog timer sends a reset signal, restarting the CPU. The flowchart of the anti-interference program during system startup is shown in Figure 2. [align=center][img=350,719]http://www.e-works.net.cn/images/127915296281093750.GIF[/img] Figure 2 Flowchart of the anti-interference program during system power-on[/align] After the system is working normally, although anti-interference measures are implemented in hardware to address voltage fluctuations caused by undervoltage of the mains voltage, excessive undervoltage can still cause the voltage comparator to flip incorrectly, leading to unnecessary external interrupts. Necessary processing is still required in the software. Upon entering an external interrupt response, the program must wait 300ms and check if the external interrupt signal is still low. If the external interrupt signal goes high, the interrupt should end and return to normal operation. If it remains low after 300ms, the CPU will then record data for protection. The 300ms period is determined based on the average undervoltage value of the power grid. VI. System Fault Tolerance Measures For microcomputer systems with extremely high data recording accuracy requirements, in addition to necessary anti-interference measures, fault tolerance is essential. Fault tolerance refers to masking the impact of faults by adding redundant resources, ensuring that the system's functionality remains unaffected even if errors or malfunctions occur. For data recording, fault tolerance involves multiple data backups. This system employs the commonly used Triple Modular Redundancy (TMR) method, which records the data three times, comparing each pair of records upon reading to determine the correctness of the recording. Only when at least two records match can the system continue to accumulate data; otherwise, an error signal is issued to alarm. Multiple recordings can effectively overcome errors that may occur with a single recording and can effectively compensate for data recording corruption caused by damage to the physical media of some storage units in the memory, thus effectively improving the reliability of the system. The specific implementation code for the above software anti-interference measures is as follows: wdi equ p3.4 wp equ p3.5 ORG 0000H ljmp main ORG 0003H ljmp int0 ORG 0030H Main:…… setb wp; AT24C02 write protection, prohibit writing, but can read normally wait0: cpl wdi; access watchdog jnb p3.2, wait0; check if the external interrupt voltage signal has become high mov r1, #10; wait 10ms after the external interrupt disappears waita: mov r0, #250 wait1: cpl wdi nop djnz r0, waitl jnb p3.2, wait0 djnz r1, waita clr wp; cancel write protection mov r0, #3 retry: mov a, #55H; after normal operation, check if the external memory is working properly; feature word #55H mov b. #XXH; #XXH is the address of a memory cell in external memory. lcall wrt24c02 mov a, #XXH lcall rd24c02 cjne a, #55H, number ……; The omitted part is the program for reading recorded data and comparing results. setb ea: Enable interrupt and enter the main loop. limp loop number: djnz r0, retry waitrest: ajmp waitrest; Wait for the watchdog to reset and restart loop: …… …… ljmp loop int0: push psw push acc mov r0, #100 intwait0: mov r1, #250 intwaitl: cpl wdi; After entering the interrupt, wait for about 100ms to prevent false interrupts caused by power fluctuations. nop djnz r1, intwaitl djnz r0, intwait0 jb p3.2, noclose; When the interrupt signal disappears after 100ms, the interrupt ends. mov r0, #ramaddreH; #ramaddreH is the address of the recorded data in the CPU, which is two bytes. mov b, #rom24c02H; #rom24c02H is the address of the cell to be written in the E2PROM. mov a, @r0 lcall wrt24e02 inc r0 mov a, @r0 mov b, #rom24c02H+1 lcall rt24c02 intwait: ajmp intwait; After the data is written, wait here until the system is completely powered off. noclose: pop acc pop psw reti …… end wrt24c02, rd24c02 are subroutines for writing and reading from AT24C02. Since the AT89C52 does not have an I2C serial interface, it uses software to simulate an I2C serial port. Due to space limitations, the relevant read and write programs are omitted here. It should be noted that after entering the external interrupt int0, a 300ms wait is performed before data saving. This time is determined based on the average undervoltage period of the mains power grid. However, it is necessary to ensure that the data to be saved is reliably written to the AT24C02 before the external power supply drops to 2.7V and before the CPU stops working. The energy meter reading in this article is represented by three bytes, and each data needs to be saved three times, requiring a total of 9 bytes to be written. Each byte write operation takes 5ms, for a total of 45ms. Considering the possibility of the longest write time, the total write time is chosen to be 100ms. Therefore, appropriate voltage divider resistors R6 and R8 or Zener diode Z need to be selected to ensure the toggling timing of the voltage comparator. This ensures that there is a 0.4s time interval between the system responding to the external interrupt during power failure and before stopping operation, ensuring that the data to be saved is reliably written to memory while minimizing unnecessary data erasure caused by false interrupts. VII. Conclusion Practical application results show that the aforementioned hardware and software anti-interference design methods and data redundancy measures significantly improve the system's reliability and fault tolerance, effectively overcome the possibility of data recording errors caused by various interference factors, ensure the accuracy of stored data, and improve the product's adaptability in industrial settings. Therefore, this hardware and software combined anti-interference design method and fault-tolerant technology is effective and feasible for data recording in intelligent recording instruments.