1. Introduction A radar video signal simulator is an important device for debugging radar signal processors. It has the function of simulating the environment and target video echo signals, and is used to evaluate the performance of radar signal processors. Since simulating the generation of radar video signals requires a large amount of computation, to ensure the real-time performance of the system, TI's TMS320C6713B DSP is used as the core component for signal synthesis, and XIUNX's Spartan-IIE series FPGA is used to control the timing logic of the system, thereby increasing the flexibility of the system design and simplifying the design. Because the TMS320C6713B DSP's core voltage is 1.2 V and its peripheral I/O voltage is 3.3 V; while the FPGA's core voltage is 1.8 V and its peripheral I/O voltage is 3.3 V, the power supply system needs to generate at least three voltages. In addition, the power-on sequence must be considered. If only the DSP or FPGA core receives power, and the peripheral I/O is not powered, the device will not be damaged, only the input/output will be lost. Conversely, if the peripheral I/O receives power but the CPU core is not powered, the transistors in the device's buffer/drive section will operate in an unknown state, which is very dangerous. Considering the high power consumption of DSPs and the requirement for multiple DSPs to operate simultaneously in this system, a linear power supply would inevitably result in significant heat loss. Therefore, a switching power supply with adjustable output voltage and high conversion efficiency is used to design the power supply system. 2. Power Supply System Design This system design utilizes the TPS54310, a low-voltage input, high-current output synchronous PWM buck converter. The TPS54310 requires only a few external components, and its 60 mΩ MOSFET switching transistor ensures a conversion efficiency exceeding 92% at a continuous output current of 3 A. By configuring external components, voltages of 0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V are generated, with a PWM frequency range of 280 kHz to 700 kHz. Overload protection is achieved through peak current limiting and thermal shutdown. The high-heat-dissipation PWP package provides better heat dissipation. Furthermore, TI provides a design tool for this series of power devices—SWIFT software—to assist in power system design and shorten the development cycle. 2.1 Core Voltage and Peripheral I/O Voltage Since the TPS54310 can generate the required 1.2 V, 1.8 V, and 3.3 V by adjusting the resistance values ​​of the peripheral resistors, the circuit diagrams for each voltage generation are shown in Figures 1 to 3. Figure 1 generates a 1.2 V voltage, Figure 2 generates a 1.8 V voltage, and Figure 3 generates a 3.3 V voltage. Since the basic principles of each circuit are similar, this paper uses Figure 1 as an example to illustrate how to adjust the amplitude of the output voltage to meet the power supply system requirements. In Figure 1, only R144 and R150 need to be adjusted to satisfy the following formula: R144 = (R150 × 0.890) / (Vo - 0.891) (1) R150 is taken as 10 kΩ. Since Figure 1 generates a 1.2 V voltage (Vo), the resistance value of R144 can be obtained from Equation 1 as approximately 26.1 kΩ. In this design, the switching frequency of all TPS54310s is set to 700 kHz. This frequency setting is calculated using Equation 2. Taking Figure 1 as an example, fSW is the configurable switching frequency, which is set within the range of 280kHz to 700kHz. SYNC must remain open. R136 = (100 KΩ/fSW) × 500 kHz (2) Therefore, the resistance of R136 is approximately 71.5 kΩ. The output filter circuit can be calculated using SWIFT software. 2.2 Sequential Power-On System The system uses TI's TMS320C67-13B DSP and Xilinx's Spartan-IIE series FPGA. Both devices require core voltage and external I/O voltage. When powering on, the core must be powered on first, followed by the external I/O; when powering off, the external I/O power supply should be turned off first, followed by the core power supply. To achieve sequential power supply of the core voltage and the external I/O voltage, the capacitor connected to the SS/ENA pin of the TPS54310 can be adjusted, and its PWRGD and SS/ENA signals can be used to meet the sequential power supply requirements. The SS/ENA pin is grounded through a small capacitor to enable, output delay, and voltage rise delay. The delay time is proportional to the capacitance value: Where: td is the output delay time (s); C(88) is the capacitor connected to the SS/ENA pin (μF); t(SS) is the output voltage rise delay time (s). In the core voltage circuit of this system, C(SS) = 0.039μF, as shown in Figures 1 and 2. In the peripheral I/O voltage circuit, C(SS) = 0.1 μF, as shown in Figure 3. According to equations (3) and (4), the td and t(SS) of the core voltage are 9.36 ms and 5.46 ms, respectively; the td and t(SS) of the peripheral I/O voltage are 24 ms and 14 ms, respectively. Connect the PWRGD pin of the TPS54310 that generates the core voltage to the SS/ENA pin. This way, even if the capacitor breaks down, at power-up, the output of the TPS54310 generating the core voltage will not reach the threshold, the PWRGD pin will output a low level, and the TPS54310 generating the peripheral I/O voltage will be in the off state until the core voltage stabilizes. This ensures that the core powers on first; when power is off, the output of the TPS54310 generating the core voltage will be below the threshold, the PWRGD pin will output a low level, and the output of the TPS54310 generating the peripheral I/O voltage will be turned off, ensuring that the peripheral I/O is powered off first. 3. Voltage Monitoring and Reset Circuit In the design of the radar video signal simulator, due to the high-frequency characteristics of the video card circuit, electromagnetic radiation from the switches and line noise will interfere with the operating voltage of the circuit components. Furthermore, DSPs and FPGAs have high requirements for their operating voltage; the deviation cannot exceed 5%. Once the operating voltage exceeds this deviation, prolonged operation can easily shorten the lifespan of the components or even burn them out. Therefore, the system design needs to monitor the operating voltage of the components in real time through a voltage monitoring circuit to ensure that the system provides a stable and normal voltage. The voltage monitoring circuit works as follows: During system power-up, the reset signal of the monitoring device remains valid, keeping the DSP and other devices in a reset state. Once all monitored voltage values ​​reach the specified threshold voltage, the reset is released, and the DSP and other devices can operate normally. During operation, if any monitored voltage falls below the threshold value, the monitoring device sends a reset signal again to reset the system. The voltage monitoring and reset circuit is implemented using TI's TPS3307-18D. The TPS3307-18D is a microprocessor power controller that can simultaneously output high-level and low-level active reset signals; it simultaneously monitors three independent voltages: 3.3 V, 1.8 V, and an adjustable voltage; it has an internal timer, and even if all monitored voltages exceed the threshold value after reset, it still requires 200 ms to exit the reset state, ensuring that the system completes initialization during the reset period. The reset signals for the DSP, FPGA, and other devices in this system are all active low. Therefore, the RESET signal of the TPS3307-18D is used for reset. RESET is used as a reset indicator to monitor the 3.3V, 1.8V, and 1.2V (amplified to 3.6V) voltages in the system. The voltage monitoring and reset circuit is shown in Figure 4. As long as the supply voltage of the TPS3307-18D is higher than 1.1V, a reset signal will be issued when any of the monitored voltages falls below its threshold value, resetting the relevant devices. In addition, the TPS3307-18D also has a manual reset signal, which can be manually reset via a reset button. 4. PCB Layout and Peripheral Component Selection Due to the high-frequency interference of the DC-DC switching circuit, proper wiring and selection of appropriate peripheral components are crucial for effectively reducing switching noise during PCB layout and peripheral component selection. The following points should be noted during wiring: the output capacitor should be placed close to the output end of the inductor; the power inductor wiring should be as wide as possible; the feedback input of the error amplifier should be far away from the power inductor, etc. To ensure the TPS54310 operates normally under heavy loads, its thermal pads should be grounded over a large area to accelerate heat dissipation. External components should include shielded power inductors and low-ESR output capacitors. 5. Conclusion The power supply system designed in this system has proven to provide a stable power supply for the radar video simulator, achieving a conversion efficiency of up to 92%, output voltage ripple of less than 0.05 V, a maximum output power of 19 W, and fast dynamic response. Furthermore, the voltage monitoring and reset circuit ensures long-term stable operation of the entire system and prevents DSP loading abnormalities caused by voltage fluctuations. Therefore, the power supply system designed in this system is also suitable for other DSP system applications.