0 Introduction Power amplifiers are widely used in many fields such as audio power amplifiers, transmission systems, servo systems, sonar detection, and vibration testing. Traditional power amplifiers use linear amplification circuits, which have low efficiency (40%~60%) and large size, thus limiting their application areas. In order to solve the shortcomings of traditional power amplifiers, switching power amplifiers have emerged[1]. At present, in the design of high-power (above 5kW) amplifier systems at home and abroad, IGBT-based full-bridge inverter topology is generally used to meet power requirements[2]. In contrast, the design scheme of high-power amplifier systems with MOSFETs as power devices[3] accounts for only a minority, and the control methods developed cannot solve the problems of current sharing control between system modules and capacitor midpoint potential control. Therefore, it is urgent to develop a high-power amplifier system based on MOSFETs to reliably improve the performance of the amplifier system. This paper proposes an inverter unit suitable for modular use in high-power amplifier systems, and details the unit's topology and digital control principle. Experimental results prove its good performance. 1 Main Circuit Topology When the traditional two-level full-bridge inverter topology is applied to a high-power amplifier system, it is difficult to use MOSFETs with higher frequencies due to the limitation of device withstand voltage, so the system performance cannot be effectively improved. Based on existing research, we adopted the five-level diode midpoint clamp inverter topology (“Five-Level NPC Inverter”, hereinafter abbreviated as “FNI”) proposed in reference [4] as the basic power unit. Figure 1 shows the FNI circuit. [img=297,219]http://www.icembed.com/UploadFiles/2006710145230734.gif[/img] Figure 1 FNI circuit The basis of this FNI structure - the NPC inverter topology - was first proposed by Nable et al. in 1981. Compared with the traditional two-level converter, it has the following advantages: In high-power systems, power devices can be directly connected in series without the need for external auxiliary circuits; the withstand voltage limit of the device is reduced to half of the DC side voltage, making the selection of devices more flexible; the harmonic components in the output waveform are greatly reduced compared with the two-level converter, reducing the burden of the filtering stage; the voltage ripple on the load is reduced, suppressing electromagnetic interference problems. 2 Comparison and improvement of control methods 2.1 Introduction to existing control schemes The advantage of the control scheme developed by Lau WH et al. in reference [4] is that it increases the equivalent switching frequency of the module output and suppresses the output harmonics; the disadvantage is that the input signal of the system cannot be used as a drive signal after PWM modulation, and more complicated calculations are required, so it cannot be well used in existing digital signal processing chips. For a detailed analysis of this scheme, please refer to reference [4]. 2.2 Principle of the improved control scheme The improved control method first doubles the carrier frequency in reference [4] to 2fC, and adjusts its bias, and then performs PWM comparison. As shown in Figure 2, the modulated signal is the drive signal. Moreover, the carrier phases of the left and right bridge arms (Leg1, Leg2) are the same, without the phase difference required by the control method in reference [4]. The advantage is that the system needs to adjust the phase difference while adjusting the switching frequency, and it is also beneficial for the system to adjust the midpoint potential of the DC side capacitor. [img=302,463]http://www.icembed.com/UploadFiles/2006710145232580.gif[/img] Figure 2 Principle comparison of the improved control scheme Figure 2 and reference [4] show that the driving signals of the switching transistors are the same, so the output waveform must also be the same. The improved control strategy can be conveniently applied to digital signal processing chips, while retaining the advantages of the control method in reference [4]. For example, the modulation of PWM on the DSP (TMS320LF2407) chip can be directly completed by the dedicated event management modules EVA and EVB, which greatly reduces the difficulty of implementing the control method. The improved control strategy also has shortcomings, namely, it does not provide a solution to the problem of unbalanced midpoint potential of the DC side capacitor. According to the experimental results, it can be found that the static error of the capacitor midpoint potential caused by the inherent resistance asymmetry of the circuit components cannot be ignored. Figure 9(f) shows the midpoint potential when the DC power supply is 400V, and a static error of 13.2V can be found. 2.3 Hazards and solutions of midpoint potential imbalance Reference [1] analyzed the influence of the DC side midpoint potential drift of the system on the output THD, as shown in Figure 3. The k value in Figure 3 represents the degree of imbalance of the midpoint. In other industrial applications, since the requirements for output waveform distortion are not high, appropriate drift of the midpoint is allowed. However, in applications such as power amplifier systems where the output waveform quality requirements are high, midpoint imbalance can become one of the important causes of output distortion. In order to overcome the degradation of output waveform quality caused by midpoint imbalance, we added midpoint balance control to the improved control method. The program flowchart is shown in Figure 4, and the block diagram of the midpoint balance control scheme is shown in Figure 5. The principle of midpoint balancing control is as follows: at the beginning of each switching cycle, the DC-side capacitor voltages are sampled to obtain VC1 and VC2 (see Figure 1). Then, a PI calculation is performed on the difference between VC1 and VC2. If the result of the PI calculation is positive, it is compared with POSREF (the maximum value of VC1 exceeding VC2 that the system can tolerate). If the comparator output is positive, it means that the midpoint drift is relatively severe. Then, the amplitude of the reference signal VS is detected. If the amplitude of VS is negative (meaning that the output is positive after the amplitude of 0 and VS passes through the comparator), the carrier frequency is increased to 2fc; conversely, if the result of the PI calculation of the voltage difference is less than NEGREF, and the amplitude of the reference signal Vs is positive, the carrier frequency is increased to 2fc; otherwise, the carrier frequency remains unchanged at fc. The function of the Switch module in Figure 5 is that if the input signal of the middle pin on the left side of the module is positive, the output on the right side of the module is the same as the input signal of the bottom left pin of the module; if the input signal of the middle pin on the left side of the module is zero, the output on the right side of the module is the same as the input signal of the top left pin of the module. [img=279,155]http://www.icembed.com/UploadFiles/2006710145233621.gif[/img] Figure 3: The effect of midpoint potential imbalance on output THD [img=281,548]http://www.icembed.com/UploadFiles/2006710145234360.gif[/img] Figure 4: Program flowchart [img=524,257]http://www.icembed.com/UploadFiles/2006710145235371.gif[/img] Figure 5: Block diagram of midpoint balance control scheme After the carrier frequency is determined, the VS function value is loaded into the comparison unit in the DSP chip event manager module, ready for PWM modulation with the carrier. After loading is completed, an interrupt reset is performed. The essence of this midpoint control method is to change the direction of midpoint current flow by adjusting the carrier frequency. By comparing the simulation results of the midpoint current flow before and after doubling the carrier frequency, we can see that: if the frequency fs of the reference signal VS is taken as the reference, before doubling the carrier frequency, the flow direction of the midpoint current ineuu changes alternately in each cycle (see Figure 6), with a frequency of 2fc; after doubling the carrier frequency, the flow direction of the midpoint current ineuu changes only once in each cycle (see Figure 7), that is, the frequency of change is 2fs. Since the flow direction of the midpoint current in the latter case is related to the amplitude of the reference signal VS, it is necessary to detect the sign of the VS amplitude before deciding whether to double the carrier frequency. [img=285,160]http://www.icembed.com/UploadFiles/2006710145236797.gif[/img]Figure 6 Simulation of midpoint current flow before carrier frequency doubling[img=272,161]http://www.icembed.com/UploadFiles/2006710145237112.gif[/img]Figure 7 Simulation of midpoint current flow after carrier frequency doubling[img=277,391]http://www.icembed.com/UploadFiles/2006710145238784.gif[/img]Figure 8 Comparison of the principle of carrier frequency doubling control scheme. As can be seen from Figure 8 and Figure 2, when the carrier frequency is doubled, the output waveform is the same as before. In the DSP (TMS320LF2407) chip, the carrier frequency can only change when the carrier amplitude is 0; therefore, the absence of a phase difference in the carrier allows the carrier frequencies of the left and right bridge arms to change simultaneously without affecting the output waveform. 3. Experimental Verification and Results This paper designs an experimental model of a single-module multilevel circuit. Its specific circuit parameters and specifications are as follows: Output full-load power 1kW; Output frequency 2kHz; DC side input voltage 400V; Basic switching frequency 100kHz. The switching transistor drive signal is provided by the DSP, and the PWM modulation of the drive signal is generated internally within the DSP. Figures 9 and 10 show the output waveforms and midpoint potential comparisons before and after using midpoint balance control, respectively. As shown in Figures 9(e) and 9(f), after using midpoint balance control, the static error of the DC side capacitor voltage is 3.2V; before using midpoint balance control, the static error of the DC side capacitor voltage is 13.2V. [img=274,194]http://www.icembed.com/UploadFiles/2006710145239833.gif[/img](a) Output waveform[img=275,178]http://www.icembed.com/UploadFiles/2006710145239738.gif[/img](b) Partial magnification of output waveform[img=276,177]http://www.icembed.com/UploadFiles/2006710145240140.gif[/img](c) Midpoint potential waveform Figure 9 Waveform before using midpoint balance control[img=276,196]http://www.icembed.com/UploadFiles/2006710145242472.gif[/img] (a) Output waveform [img=279,199]http://www.icembed.com/UploadFiles/2006710145243876.gif[/img] (b) Partial magnification of output waveform [img=300,195]http://www.icembed.com/UploadFiles/2006710145243811.gif[/img] (c) Midpoint potential waveform Figure 10 Waveform after applying midpoint balance control 4 Conclusion This paper analyzes the topology and digital control scheme of switching power amplifiers. In the control scheme design, a PWM control technology suitable for a five-level diode midpoint clamp inverter topology is introduced, which can improve the equivalent switching frequency of the output and reduce the drift of the DC side midpoint potential, thereby improving the quality of the system output waveform. The FNI power modules in the paper can be interleaved to increase the total power of the system and the number of output waveform levels. This not only meets the requirements of expanding the power level of the system, but also reduces the output distortion of the system. For detailed analysis, please refer to reference [1]. Of course, there are still many problems to be solved, such as the dead-time compensation problem of the multi-level inverter circuit and the current sharing problem among multiple modules. These will be the focus of the next research work.