[b]1 EASY CORE PLC Chipset[/b]EASY CORE is a core chipset loaded with the EASY embedded PLC software platform for designing PLCs. Its internal structure block diagram is shown in Figure 1. [img=412,220]http://img.hc360.com/ec/info/images/200810/one_20081008130302923.jpg[/img] 1.1 EASY CORE Core The core uses the C8051F040 hybrid high-performance microcontroller, which has 64 I/O port pins, one CAN2.0B integrated controller, a 12-bit ADC, PGA and analog multiplexing switch, two 12-bit DACs, 64 KB of programmable Flash memory, 4352 (4096+256) bytes of RAM, SPI, SMBus/I2C, two UART serial interfaces, five 16-bit general-purpose timers, a programmable counter/timer array with six capture/compare modules, an on-chip watchdog timer, a VDD monitor, a temperature sensor, etc., and operates within an industrial temperature range of -45℃ to +85℃ using 2.7 to 3.6... The operating voltage is V. The on-chip counter/timer, serial bus, hardware interrupt, ADC conversion start input, comparator output, and other internal digital signals of the microcontroller can be configured to be output on I/O pins by setting the switch crossover control register. Users can select the combination of general-purpose port I/O and required digital resources according to their specific applications. The kernel uses a real-time operating system and loads a monitoring program in ladder diagram language compatible with FX2N PLC. The instruction system and communication format are compatible with FX2N PLC. Therefore, it can be programmed using FX2N PLC software or monitored using general-purpose configuration software. 1.2 User-Driven Development Interface Users can embed assembly programs to perform specific functions according to the interface specification, implementing I/O point configuration, AD/DA, and other special functions. ① The embedded program code is stored at addresses E000H～F7FFH. ② The interrupt sources available to users are listed in Table 1. [img=375,388]http://img.hc360.com/ec/info/images/200810/one_20081008130253402.jpg[/img] ③ User-accessible area in the bit register region (20H～23H). ④ User-accessible area in the direct addressing register region (58H～67H). ⑤ User-accessible area in external RAM (3600H～3FFFH). ⑥ PLC resource area (0000～5080H), accessible by both system and user programs. The bit variable area and word variable area are listed in Tables 2 and 3, respectively. [img=344,433]http://img.hc360.com/ec/info/images/200810/one_20081008130258305.jpg[/img] **2 Application Examples** Taking an 8-input, 7-output PLC design as an example, the design process of a dedicated PLC is explained. **2.1 Hardware Circuit Design** The hardware circuit consists of a chipset, power supply circuit, input interface circuit, output interface circuit, and communication interface circuit. 2.1.1 EASY CORE Chipset Peripheral Pins The pin distribution of the EASY CORE chipset is shown in Figure 2. [img=196,520]http://img.hc360.com/ec/info/images/200810/one_20081008130256406.jpg[/img] [b]（1）Special Purpose Pins[/b] P0.0, RXD of Serial Port 1, used for downloading programs. P0.1, TXD of Serial Port 1. P0.2, RXD of Serial Port 2, used for RS4.85 communication. P0.3, TXD of Serial Port 2. P4.5, PRO, embedded program download, active low. P4.4, RUN/SET. CANRX, CANTXD, CAN bus interface. [b]（2）User Application Pins[/b]AIN0.0～AIN0.3, analog input; DAC0～DAC1, analog output; P1, P2, P3, P0.4～P0.7——digital I/O, which can be connected to the PLC's input/output buffer through the interface program. [b]2.1.2 Input/Output Interface Circuit[/b]Input Interface Circuit: Input points are X0～X7 (only one is shown in the figure). The input interface uses an opto-isolator TLP180 to prevent external interference. The interface circuit is shown in Figure 3. P3.0 is a high-level voltage of 3.3V. [img=358,176]http://img.hc360.com/ec/info/images/200810/one_20081008130258001.jpg[/img]Output Interface Circuit: Output points are Y0～Y7 (only one is shown in the figure). The output signal drives the output relay or transistor through 2003, as shown in Figure 4. The ULN2003AN is a 7-channel driver. [img=422,203]http://img.hc360.com/ec/info/images/200810/one_20081008130252122.jpg[/img] **2.2 Software Design** The core functions of PLC instruction interpretation and communication with the host computer are completed by the EASY CORE kernel; the user program only needs to compile a small number of interface programs according to the interface specification and user design requirements. The user program mainly connects the external interface circuit with the input and output buffers of the kernel software. It reads P3.0～P3.7 (X0～X7) and sends it to the corresponding RAM-PX, and outputs the data from RAM-PY (Y0～Y6) to P1.0～P1.6 (Y0～Y6). The main program structure is shown in Figure 5. [img=304,190]http://img.hc360.com/ec/info/images/200810/one_20081008130255770.jpg[/img] (Main program omitted - Editor's note) **3 Conclusion** Chipset-based embedded PLCs can effectively compensate for the shortcomings of general-purpose PLCs in the low-end market and are closely integrated with process objects. As long as the anti-interference design problem of the circuit is solved, embedded PLCs have a large market prospect. Currently, the author has successfully applied it to the transformation of gantry milling machines.