Suppose the display terminal is a Digital Micromirror Device (DMD) monitor. This monitor processes the image signal of each pixel of the computer through Digital Light Processing (DLP) and stores it in an SDRAM bidirectional buffer. When a frame of image is received, the internal data processing circuit simultaneously excites the micromirrors corresponding to each pixel to complete the display of a frame of image. The peak digital drive voltage of the DMD monitor does not exceed 33.5V, the electromagnetic radiation is very low, and the simultaneous driving of each micromirror forms mutually interfering outward radiation signals, making decoding extremely difficult, thus making it a monitor without information leakage. At this time, the radiation from the video cable dominates the radiation of the entire video path. If the video signal is processed before it is transmitted to the monitor through the video cable, electromagnetic radiation and information leakage can be effectively reduced. [b]1 Video Information Leakage Mechanism and Solutions 1.1 Leakage Mechanism in Video Information Transmission[/b] In the computer video path, information transmission mainly takes two forms: parallel transmission and serial transmission. Currently, most video information is transmitted serially. When the wavelength of the serial signal is comparable to the physical length of the video cable, the video cable acts as an antenna, easily generating high-intensity electromagnetic leakage of useful information. This makes it relatively easy to achieve time-division, frequency-division, and azimuth reception of serial signals. Therefore, serial video information is easily stolen and reproduced. In parallel transmission, because the data lines are very close together and the transmitted signals have the same or similar frequencies, interception is much more difficult. However, if the R, G, and B serial analog video signals are converted into digital signals and then transmitted directly without processing, what is transmitted simultaneously are still different bits of a pixel. Therefore, from a pixel perspective, it is still considered serial transmission. If the transmitted image only has black and white, then the data on the parallel transmission cable at any given moment will be all "1"s or all "0"s. That is, all signal lines in the parallel cable have the same waveform, so there is no need to receive each signal line separately. In this case, the video cable is similar to serial transmission, and the useful information can be easily stolen. 1.2 Pixel-Based Parallel Transmission To effectively reduce the possibility of video signal interception, a format conversion is performed on the video signal before it is transmitted through the video cable. This allows multiple pixels to be transmitted simultaneously on the parallel cable, achieving true parallelism, i.e., pixel-based parallel transmission. In this parallel transmission method, even if the receiver receives the radiated information, it cannot reproduce the information because it cannot distinguish the order of the pixels. The information leakage prevention system designed in this paper achieves simultaneous transmission of multiple pixels by processing the format conversion of the video signal. Figure 1 is a schematic diagram of the video information format conversion principle. The input data is a digital video signal obtained after A/D conversion from a serial analog video signal. When the system receives information, it receives it pixel by pixel in sequence, at which point the data is in "pixel packet" format. After processing by the format conversion module, these video signal data received in "pixel packet" format are converted into output data arranged in "bit plane" format. At this point, multiple pixels of data are transmitted on the parallel cable. The "bit plane" format video data is transmitted to the display end and then restored to "pixel packet" format by the format conversion module. The sequentially received "pixel packet" format data can be described using the following set method: If the system receives n pixels, then D represents the received video signal, S represents the sequential relationship between the elements in D, and the signal color number is 23m, that is, R, G, and B each have 2m gray levels, then: Similarly, the output data after conversion to "bit plane" format can also be described using the same set method: E represents the data of a frame of image after format conversion, F represents the sequential relationship between the elements in E, then: Converting the video information from the form represented by set D to the form represented by set E is the work to be completed by the transmission data format conversion, that is, it requires first outputting the first bit of binary data of all pixels, then outputting the second bit of binary data of all pixels, until finally outputting the last bit of binary data of each pixel. Therefore, "bit plane" data is a set of data of three colors with the same "weight" of n pixels. [b]2 System Hardware Design 2.1 Overall Scheme Design[/b] Based on the principle of pixel parallel transmission proposed above, an FPGA-based anti-video information leakage system is designed. Figure 2 shows the hardware design block diagram of the system. The entire system consists of an acquisition adapter card and a display adapter card. The high-speed video-dedicated A/D converter adopts the high-performance AD9883A from AD company. Its main features are: (1) a bandwidth of up to 300MHz and a conversion rate of 140MSPS. (2) three independent input signal ranges of 0 to 1.0V, which are very suitable for sampling video signals. (3) It provides an I2C bus interface, etc., to adapt to various applications. The working principle of the system is: the video signal from the graphics card is input to the acquisition adapter card. The A/D converter on the acquisition adapter card converts the three analog video signals of R, G, and B into three parallel 8-bit digital signals respectively. At the same time, it performs phase repair and amplitude compensation for the horizontal and vertical synchronization, so that it becomes a standard horizontal and vertical synchronization signal. Then, the signal is sent to the FPGA. At the same time, under the control of the state machine, the video information in units of pixels is converted into a "bit plane" format. After signal processing, the signal is transmitted to the display adapter card via a parallel transmission cable. The display adapter card is responsible for restoring the "bit plane" information to pixel format and converting the three 24-bit digital video signals into analog signals via a D/A converter before sending them to the display device for display. [b]2.2 Electromagnetic Compatibility Design 2.2.1 Signal Integrity Design[/b] The digital video signals in the system have high requirements for transmission delay. When wiring, the routing paths should be roughly consistent and as short as possible to meet the transmission delay requirements. The placement of decoupling capacitors should be arranged reasonably, as close as possible to the power supply to be decoupled. The wiring around the AD9883A chip and ADV7125 chip should be as short as possible, and the surrounding components should be arranged as compactly as possible to reduce the current loop area and thus reduce electrostatic interference. When placing vias, care should be taken not to make them too dense to avoid damaging the mirror layer. The resistors, capacitors, inductors, and IC chips used in the adapter card are all surface-mount components, which helps to suppress electromagnetic interference. 2.2.2 Power Integrity Design The A/D and D/A converter chips used in the system have strict power requirements. Besides requiring separate analog and digital power supplies, the AD9883A also needs a dedicated power supply for the PLL circuit, while the FPGA power supply requires both core power and power supplies for the digital output pins. Therefore, the power supply design of the entire system is a significant challenge. Here, two LT1764 chips are used for the two power supplies of the FPGA, two TPS76333 chips for the two power supplies of the AD9883A, and one TPS76333 for the ADV7125. Both adapter cards adopt a four-layer board structure, with the top and bottom layers serving as signal routing layers, and the middle layers as ground and power layers, respectively, to ensure a good power environment for high-speed system operation. 3 System Logic Implementation and Simulation The FPGA chip used is the Altera Cyclone series chip EP1C6Q240C8. The Cyclone series chips are based on a 1.5V, 0.13μm process, featuring a phase-locked loop (PLL) and a dedicated DDR interface, supporting multiple I/O standards. They embed many dedicated hard-core modules and are widely used in System-on-a-Chip (SOPC). This system processes high-speed image signals with a working clock of nearly 100MHz. To achieve better routing and system performance, the clock signal must pass through a PLL to reach the global clock routing network. This design utilizes Altera's Maga Wizard to set Cyclone PLL parameters and generate IPcores, solving the signal delay problem while also meeting the setup and hold time requirements for reading video signals. Figure 3 shows the waveform after phase-shifting the input point frequency clock PXCLK_AD using the FPGA's internal PLL. In the figure, pxclk is the same frequency as the point frequency and, after phase repair and amplitude compensation, is used as the system reference clock. delayclk is a division of the point frequency and is used as the delay clock. 3.1 Video Information Format Conversion Module In the acquisition adapter card, video information is converted from "pixel packet" format to "bit plane" format. This can be accomplished by an n×m matrix conversion circuit with an input data bus width of m bits and an output data bus width of n bits. During system operation, n consecutive inputs are performed each time, i.e., reading in n pixels of data, followed by m consecutive outputs, i.e., writing these data to their respective storage locations corresponding to the m bit planes. The principle of the format conversion circuit is shown in Figure 4. An n×m D flip-flop array, along with corresponding input and output latch circuits and a state machine control circuit, can achieve n×m data format conversion. When the i-th pixel is input, the input data state machine triggers the i-th row of D flip-flops, and the j-th grayscale information of the i-th pixel is stored in the (m-1-j)-th D flip-flop in the i-th row (i=1, 2, ..., n, j=0, 1, ..., m-1). After all n pixels have been input, the n×m bits of binary information are stored in the n×m D flip-flops. At this point, the D flip-flops in the i-th row store the m-bit grayscale information of the i-th pixel, i.e., "pixel packet" format information, and the D flip-flops in the j-th column store the (m-1-j)-th grayscale information of the n-th pixels, i.e., "bit plane" format information. The output data state machine outputs the data from a certain column of D flip-flops in a specific order, thus achieving the output of "bit plane" data. The principle of converting video information from "bit plane" format to "pixel packet" format is similar to the matrix circuit described above, and will not be discussed further here due to space limitations. With a resolution of 1024×768 and a refresh rate of 75Hz, the frequency is 78.75MHz. Since the data transmission speed is inversely proportional to the number of bits transmitted, if n 3.2 Synchronization Signal Delay Module The synchronization signal is a pulse train of a certain frequency, which has a strict synchronization relationship with the video signal. Its frequency is related to the display resolution and screen refresh rate set by the graphics card. During the video information format conversion process, the video information is delayed by approximately nine frequency cycles. To ensure that the timing relationship between the video information and the horizontal and vertical synchronization signals remains intact when the video information enters the display device, both horizontal and vertical synchronization signals need to be processed by a delay module. Figure 5 shows the horizontal synchronization signal delay circuit diagram in the acquisition adapter card. This system consists of two adapter cards, and the horizontal and vertical signal delay circuits in the two adapter cards are similar. 3.3 System Top-Level Module After the entire anti-video information leakage system design is completed, its top-level module is shown in Figures 6 and 7. In the figures, SCI and SDA are used to initialize the AD9883A chip, and DATA_RDY is a custom video information conversion completion signal. Both adapter cards have format conversion circuits. After two format conversions, the video information is finally restored to the initial "pixel packet" format data. With the input frequency PXCLK_AD set to 78.75MHz, the results of the integrated simulation of the two top-level modules using Quartus II are shown in the figure. In the figure, the three sets of data are in "pixel packet" format, "bit plane" format, and "pixel packet" format, respectively. It can be seen from the figure that the video information is restored to its original form after two conversions. The line and field signals also have a certain delay, but maintain good synchronization with the video information. This indicates that the pixel-based parallel transmission method is feasible. Under the premise of using a DMD display as the terminal display device, a computer-based video information leakage prevention system based on a Field Programmable Gate Array (FPGA) and using a pixel-based parallel transmission method as its core can achieve simultaneous transmission of multiple pixels. The receiver finds it extremely difficult to distinguish the display order of each pixel from the received radiation information, thus preventing the information from being reproduced. This effectively prevents the interception of video information and enhances information security.