Design of a numerically controlled delay based on a field-programmable gate array (FPGA)

This paper presents a design method for a numerically controlled delay based on a Field-Programmable Gate Array (FPGA). First, it details the method of achieving controllable delay using cascaded counters. Next, it discusses improvement schemes for the numerically controlled delay under different delay ranges. Finally, it analyzes the delay error and delay accuracy. The external interface of the delay is designed in imitation of the AD9501. Introduction Utilizing hardware description languages combined with programmable logic devices (PLDs) can greatly facilitate the design of digital integrated circuits. This paper introduces a numerically controlled delay designed using VHDL hardware description language combined with a Field-Programmable Gate Array (FPGA). Under the action of the clock clk, the delay amount is input from the 8-bit data lines, and the data is latched when LATCH is high, enabling arbitrary delays on the trigger pulse TRIG. Since different delay ranges require different FPGA resources, this paper details the case where the maximum delay amount is less than the trigger pulse period. The software programming and debugging of this delay unit were completed in the Muxplus II environment. The system design uses Altera's EPF10K30AQC208-3 and EPCI441 dedicated circuits, combined with a DSP, and applied to the control part of the radar target simulator to simulate target distance. [b]2 Design Principles[/b] The numerically controlled delay circuit designed by this author uses three serial counters. Since the delay begins on the rising edge of the trigger pulse TRIG, counting is performed on the rising edge of the clock. Considering the limitations of VHDL's clock description, counter 1 generates a synchronization pulse SYNC with a width of Tclk. The high level of SYNC triggers cflag, and cflag is cleared after the delay ends. Counter 2 calculates the delay length; counter 3 calculates the pulse width of the output pulse OUTPUT, and both counters 2 and 3 are cleared at the end of the counting process. The external interface circuit of the delay circuit is shown in Figure 1, and the block diagram is shown in Figure 2. The entire circuit design uses synchronous clock counting to minimize glitches and race conditions caused by local clock instability. [img=196,225]http://image.mcuol.com/News/080227105805280.jpg[/img][img=386,127]http://image.mcuol.com/News/080227105805541.jpg[/img] This CNC delay latches data when the level is low and changes the value of the internal register when the level is high (opposite to the data latch level of the AD9501 CNC delay). Normally, the trigger pulse coincides with the rising edge of the clock. If the input trigger pulse is inconsistent with the clock, the delay of the entire circuit will have a certain error. The timing simulation is shown in Figure 3. The delay amount is determined by the data on the data bus data8 when dlyLH is high. The VHDL hardware description language program for this CNC delay is as follows: [img=438,586]http://image.mcuol.com/News/080227105810252.jpg[/img] [img=522,1038]http://image.mcuol.com/News/080227105810983.jpg[/img] In this program, cntl is the delay amount, cnt2 is the width of the output pulse, and cflag is the start of counting flag. When the period of the trigger pulse is greater than 256xTclk, the maximum delay amount is 256xTclk. If the period of the trigger pulse is less than 256xTclk, the maximum delay amount is Tclk-Toutput (Toutput is the width of the output pulse). [img=600,168]http://image.mcuol.com/News/080227105811514.jpg[/img] In fact, in practical applications, the frequency of the output pulse after the delay is not the same as that of the input trigger pulse. For example, when designing a radar target simulator, it is required to generate a series of 7-division clocks after the delay, as shown in Figure 4 (11 7-division pulses are generated after the delay, with a duty cycle of 2:5). [img=600,188]http://image.mcuol.com/News/080227105812735.jpg[/img] To generate the above trigger pulse, simply change the length of counter 2 and add a case statement to the program. [img=498,163]http://image.mcuol.com/News/080227105813286.jpg[/img] [b]3 Discussion on Delay Range[/b] 3.1 Delay Range Less Than Trigger Pulse Period In this case, simply increase the number of bits at the data input terminal. However, in general, the number of bits at the data input terminal is fixed. In this case, a multi-bit data register can be defined internally within the FPGA. Taking a delay range of 224xTclk as an example, a 24-bit data register is defined internally within the FPGA, and three address lines dlyLH1, dlyLH2, and dlyLH3 are defined. Data is sent to the data register in three installments via an 8-bit data bus. The data sending time should be after the end of the previous pulse delay and before the arrival of the next pulse. The procedure for sending data into the register is as follows: [img=463,306]http://image.mcuol.com/News/080227105813397.jpg[/img] [img=514,164]http://image.mcuol.com/News/080227105813286.jpg[/img] 3.2 Delay Range Greater Than Trigger Pulse Period This situation is quite common in practical applications. For example, in the design of radar simulators, the range of the simulated target is generally very large, so the delay of the output delay pulse will be greater than one trigger pulse period. In this case, considering FPGA resources, a multi-path delay merging method can be adopted. Taking a delay range of less than 4 periods as an example, the specific timing is shown in Figure 5. [img=403,159]http://www.21ic.com/info/images/iie/200609/7/7i.jpg[/img] The SYNC signal is divided by 4 to generate 4 frequency-divided signals. Four delay circuits are designed inside the FPGA. SYNC1, SYNC2, SYNC3, and SYNCA serve as trigger signals for the four delay circuits. Each delay circuit follows the design method of the first delay range, and the output trigger pulse is sent to the output terminal OUTPUT through four OR gates. It is worth noting that each delay circuit must define a data register with the same number of bits as DATAREG. The delay data is sent to the internal register at the start of the delay. The most critical aspect of using the multi-channel delay merging method is to generate accurate frequency-divided pulses. If the generated pulse has glitches, or if there are design flaws in the circuit, the entire delay system may not function properly. [b]4 Delay Error Analysis[/b] Taking a delay range smaller than the trigger pulse period as an example, the fixed delay and delay error are analyzed. The delay timer in the Muxplus II environment has a delay of 8.2 ns from the input clock Tclk to dlytrig; the width of the SYNC signal is Tclk. Therefore, when the rising edge of the trigger pulse aligns with the rising edge of the clock signal, the inherent delay of this delay circuit is 8.2 ns + 2Tclk. However, in general, the rising edge of the trigger pulse and the rising edge of the clock are not synchronized. Based on the relationship between them, the maximum delay error T satisfies: 0

# Field Programmable Gate Array | Numerical Control Delay

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Design of a numerically controlled delay based on a field-programmable gate array (FPGA)

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