The embedded control system was developed to realize the operation and control functions of a certain type of military vessel simulation training system. Based on dual-use (military and civilian) automatic technology, the system adopts a modular design, allowing for easy upgrades and modifications to adapt to vessel improvements and modifications, thus demonstrating broad application prospects. The embedded control system is the control center of the vessel simulation training system, and its anti-interference design is a crucial aspect of the system's development, directly affecting its stable operation. Clock Circuit Anti-interference Design The clock circuit generates the CPU's operating timing pulses, which are critical for normal operation. Interference with the clock signal will disrupt the CPU's operating timing, causing the system to malfunction. The clock signal is not only the most sensitive part to noise interference but also a major noise source for microcontroller systems. The microcontroller's clock signal is a high-frequency square wave, composed of a sine wave of the same frequency and its harmonics. The higher the frequency, the easier it is to be transmitted and become a noise source. Furthermore, the higher the clock frequency, the higher the information conversion frequency on the information transmission line, leading to increased crosstalk, reflection interference, and common impedance interference. Therefore, while meeting system functional requirements, the clock frequency should be reduced as much as possible. This is extremely beneficial for reducing electromagnetic emissions and improving the system's anti-interference performance. The anti-interference design of the embedded control system clock circuit mainly involves the following steps: ● The clock pulse circuit should be placed as close to the CPU as possible, with short and thick leads. ● The oscillation circuit should be surrounded by a ground wire, and the crystal casing should be grounded. ● The crystal oscillator circuit capacitors should have stable performance, accurate capacitance, and be kept away from heat-generating components. ● High-current signal lines and power transformers on the printed circuit board should be kept away from the crystal oscillator signal connections. ● For external clock source circuits, filter measures should be taken for their chip power supply. ● When the clock circuit provides clock signals to other chips, isolation and driving measures should be adopted. Reset Circuit Design In embedded control system design, the design of the reset circuit is very important because the microcontroller application system frequently requires entering a reset state. Therefore, the reset circuit must work accurately and reliably, and its reset state is closely related to the reset state of the application system. The microcontroller's reset is achieved through an external circuit. After the clock circuit starts operating, the microcontroller initializes and resets itself once a high level is observed on the RST pin for at least 24 oscillation pulses (2 machine cycles). To ensure reliable system reset, the RST pin must be kept high for at least 10ms during the reset circuit design. As long as RST remains high, the MCS-51 microcontroller cycles through resets. When RST transitions from high to low, the microcontroller begins executing the program from address 0000H. During the reset period, the ALE, PSEN, P0, P1, P2, and P3 pins output high levels, meaning all quasi-bidirectional ports are in input mode, and 07H is written to the stack pointer SP (setting the stack bottom to 07H). Simultaneously, the program counter PC and other special function registers are cleared (except for indeterminate bits). The reset does not affect the microcontroller's internal RAM state; however, during a power-on reset, the RAM data lost during power-off is replaced by random numbers due to the re-energization of power. The initial reset state of the microcontroller after reset is shown in Table 1. [img=492,252]http://image.mcuol.com/News/080318120839630.gif[/img] The system uses a program execution monitoring circuit to meet the system's reset requirements. Program execution monitoring is usually achieved using various types of program monitoring timers (WDTs), commonly known as "watchdogs." WDTs ensure that the program can enter a reset state promptly if it malfunctions, such as crashing. There are generally three types of WDTs: WDT functional units internal to the microcontroller; WDT circuits for μP monitoring and control devices; and WDT circuits externally set to the microcontroller. In this system, we use an externally set WDT circuit. Figure 1 shows a schematic diagram of the external WDT circuit. The WDT is a timer with a clear terminal CLR and an overflow signal OF output. The timer consists of a pulse source PWDT, a loop counter, and a monostable circuit. The PWDT provides the counting pulse for the loop counter, and the monostable multivibrator converts the loop counter overflow signal into the microcontroller's reset pulse WRST. Figure 1 shows a schematic diagram of the external WDT circuit for the microcontroller. The interface circuit between the MAX813L and 8031 ​​used in the system is shown in Figure 2. This circuit can implement watchdog and power failure monitoring functions. The MAX813L is a chip with WDT and voltage monitoring functions. Its WDT function can generate a reset output if the input does not change within 1.6s. At the same time, the voltage monitoring function can ensure a low-power output when the power supply voltage is lower than 1.25V. In addition, the MAX813L can automatically generate a 200ms wide reset pulse upon power-on and has a manual reset function, which can provide good protection for the CPU. Figure 2 shows the connection diagram between the MAX813L and the 8031 ​​microcontroller. By directly connecting WO and WR, once the program crashes, WO will become low and remain low for more than 140ms. This signal will reset the MAX813L, clear the watchdog timer, and make the RST pin output a high level, thus resetting the microcontroller. After 200ms, the microcontroller exits the reset state and resumes normal program execution. The aforementioned hardware "watchdog" is used to resolve infinite loop faults in the main program. For interrupt faults occurring in the program, the system uses a software "watchdog" to detect and handle interrupts. The software "watchdog" sets variables t0 and t1 in the main program. When T0 experiences an interrupt, t0 is incremented by 1; when T1 experiences an interrupt, t1 is incremented by 1. The current values ​​of t0 and t1 are recorded at the beginning of the main program's functional modules, and the counter's counting period is set to be less than the functional module's execution time. Thus, the counter will definitely interrupt during the functional module's execution cycle. By detecting this change at the functional module's exit point, it is determined whether an interrupt shutdown has occurred, and fault handling is performed. Anti-interference design of the controller bus Since the microcontroller used in the system cannot meet the system requirements using only its own functions, external interface chips are needed to extend its functionality. The bus is the channel for data exchange between the microcontroller and various external interface chips. The reliability of the bus directly affects the reliability of the entire system. The system mainly adopts the following measures to improve the bus's anti-interference capability: A tri-state gate bus driver is used to provide anti-interference capability. The bus driver uses the TTL type tri-state buffered gate circuit 74LS245, which can be used for bidirectional driving. The tri-state gate buffer reduces the impact of distributed capacitance and inductance on bus operation. Up to 400 chips can be connected on the bus, and its anti-interference capability is approximately 10 times greater than that of an OC (open collector) gate, capable of driving 100m of wire. A Schmitt trigger circuit is added to the bus receiver as a buffer for anti-interference. Adding a Schmitt trigger circuit near the printed circuit board socket at the receiver end can filter out external noise and improve the bus's anti-interference performance. The 8031 ​​bus is composed of tri-state output devices, which are unstable when all tri-state drivers (D) are at high impedance. Pull-up resistors can be used to connect the bus to the power supply through a 5kΩ resistor R, bringing it to a stable high potential momentarily, thereby enhancing anti-interference capability. Improve bus load balance and enhance system reliability. Add bypass capacitors to dynamic RAMs, and connect a 0.1μF capacitor to ground on the power supply terminal of each dynamic RAM chip to suppress interference. Simultaneously, minimize the power and ground traces on the printed circuit board. In static RAM circuits, ensure uniform current flow across the printed circuit board jumpers, preventing areas with large current fluctuations from frequently moving across the printed circuit board. Reduce the peak noise voltage generated during memory access. Interface circuit anti-interference design 1. Anti-interference design of the forward channel: The forward channel is the signal acquisition channel for the microcontroller application system, from signal sensing and transformation to microcontroller input. The forward channel design mainly considers the anti-interference design of integrated operational amplifiers, anti-interference assembly of op-amp circuits, anti-interference design of multiplexers, and anti-interference design of A/D conversion circuits. The anti-interference design of integrated op-amps includes the control of internal and external noise of the integrated op-amp circuit and common-mode noise control of the integrated op-amp circuit. Anti-interference assembly measures for operational amplifier circuits include: ● Enclosing the high input impedance section with copper foil wire and connecting it to the low impedance section of the circuit at the same potential. Since the potential of the isolation wire and the high input impedance section is close, the leakage current is very small. ● Using a terminal block made of highly insulating polytetrafluoroethylene (PTFE) and mounting it on the printed circuit board. The high input impedance sections are also connected to this terminal block to ensure high insulation and shock resistance of the circuit. ● Connecting potentiometers and fixed resistors in parallel, using large-size wire-wound potentiometers whenever possible. Anti-interference measures for multiplexers also focus on noise suppression, mainly including: ● Connecting a common-mode choke at the input of the multiplexer to suppress high-frequency common-mode noise introduced by external sensors. ● Using a double-shielded connection for the isolation transformer of the multiplexer to cut off the path for high-frequency noise and pulse noise transmitted by the transformer's distributed capacitance. ● Using optocoupler isolation between the microcontroller and the digital-to-analog converter to prevent high-frequency noise generated by each from intruding into the other. ● Narrowing the bandwidth of the preamplifier with capacitors to reduce its response to high-frequency noise and suppress high-frequency noise. A/D converters are highly sensitive to even small noise in analog signals. To suppress this interference, the following measures are primarily taken: ● Use metal-cased polypropylene capacitors as integrating capacitors, wrap them in copper foil, and ground them separately. ● Connect a bypass capacitor to each integrated circuit to reduce the high-frequency impedance of the power supply, overcoming internal chip noise and power supply noise. ● Adjust the gain distribution of each stage of the circuit, and connect simple low-pass filters before each operational amplifier stage to continuously attenuate noise during transmission. Simultaneously, add an anti-aliasing filter between the operational amplifier circuit and the ADC input circuit to reduce operational amplifier noise. ● Design an ADC input protection current. Because the circuit uses a ±15V operational amplifier to drive a ±5V CMOS ADC, it is prone to excessively high input voltage. We add a 78L05 three-terminal voltage regulator between the +15V and +5V power supplies, and between the -15V and -5V power supplies. Additionally, connect two Schottky diodes at the ADC input to prevent excessive current. ● Decouple the power supply separately, isolating the sampling clock circuit from the system's digital circuitry and noise sources within the digital circuitry to minimize coupling between the digital output and the sampling clock signal. 2. Backward Channel Anti-interference Design The backward channel's anti-interference primarily involves the D/A converter (DAC) anti-interference design. The system mainly employs the following steps: ● Use a multi-layer PCB (printed circuit board) with large ground and power lines. During PCB assembly, sockets are not required; the circuit is directly mounted on the PCB. Separate the analog and digital power supplies, ground them separately, and decouple them separately. Separate the analog and digital grounds and place them close to the planar ground. ● Connect a 10μF tantalum capacitor and a 0.01μF chip capacitor in parallel between the power supply and the corresponding ground. Place the decoupling capacitor close to the pins of the D/A converter to decouple the power supply. ● Use a segmented power supply structure, replacing the highest-weighted current sources with equivalent current sources. Instead of driving one highest-weighted current source (maximum current) with one bit, drive multiple equivalent current sources to suppress short-time pulse waveform interference caused by inconsistent switching times. ● Connect a 50Ω resistor in series between the DAC input line and the driver output line to reduce overshoot and transient interference on the digital input. ● Connect a 5pF capacitor across the output and ground to suppress spike interference caused by instantaneous changes in digital input and asynchronous switching. 3. Anti-interference design of the human-machine interface The anti-interference design of the human-machine interface mainly includes the anti-interference design of the button circuit and the LED display interface. The anti-interference of the system's buttons is to use multiple consecutive samples in the button confirmation cycle to determine the button action. The button confirmation cycle should be greater than the button change cycle and much smaller than the stable cycle of one button press. The LED display section of the system uses the 5-bit seven-segment LED decoder/driver chip MC14489. Since the LED interface is easily interfered with by other electronic devices during application, causing changes in the display, we also need to design it for anti-interference. Add a dual-capacitor filter to the power supply section, and then, in conjunction with the software design, add a delay between the two steps of the control pin program to concentrate the spectrum of the normal signal to the low-frequency part, so as to better control the minimum level width required by the filter capacitor.