Abstract: The design and programming of a lift state controller based on the Finite State Machine (FSM) is carried out in VHDL of Max+Plus II. The core procedure is synthesized and optimized through Synplify Pro. The simulation and experimental results on an intact three-lift control system demonstrate that this design method is effective and flexible. Key Words: FSM , VHDL, Synthesis 1 Introduction Max+Plus II is an FPGA/CPLD development integrated environment provided by Altera, which can independently compile simple VHDL programs. However, the automatic elevator control program is a complex state machine description, and Max+Plus II cannot independently complete the synthesis and compilation of this program. Synplify Pro is an FPGA synthesis tool from Synplicity for complex programmable logic design. It offers unparalleled circuit performance and the most efficient resource utilization for programmable designs. Its unique circuit debugging and optimization functions and extremely fast computing speed make it a popular synthesis tool in the industry. Synplify Pro's unique FSM synthesizer can automatically identify finite state machines and select the best encoding method based on constraints. By using the interface in Max+Plus II, Synplify Pro can be used to synthesize and optimize elevator control programs, which can greatly improve design efficiency. Simulation and experimental results have confirmed the effectiveness of this method. 2 System Design 2.1 Overall System Design In the design of the elevator control system, the core is the design of the elevator operation state controller. In order to highlight the transition relationship between states and make the elevator rise and fall at the same rate, the main considerations are: (1) manual control of the elevator; (2) display of the elevator's operating status; (3) safety control of the elevator; (4) strategy control design of the elevator. The elevator state controller is implemented using a state machine. The basic model is as follows: (1) Each elevator entrance is equipped with an up/down request switch, and the elevator is equipped with a stop request switch for the floor the customer has reached; (2) An elevator location indicator and an elevator operation mode (ascending or descending) indicator are provided; (3) The elevator is initially in the first floor with the door open, and the elevator ascends (descends) one floor every second; (4) An asynchronous set port is designed to return to the initial state when the system is abnormal; (5) When the elevator reaches the floor with a stop request, the elevator door opens after 1 second, and after 4 seconds of opening, the elevator door closes (the door opening indicator light goes out), and the elevator continues to run until the last request signal is executed and then stops at the current floor; (6) It can remember all request signals inside and outside the elevator and respond in order according to the elevator operation rules. Each request signal is retained until it is executed and then eliminated; (7) Elevator operation rules: When the elevator is in ascending mode, it only responds to the up-floor request signal higher than the elevator's location, executing them one by one from bottom to top until the last up-floor request is executed; if there is a down-floor request on the upper floor, it directly ascends to the highest floor with a down-floor request and then enters descending mode. When the elevator is in descending mode, it is the opposite of ascending mode. The entire elevator control system will be implemented by a CPLD. The peripheral circuits mainly include: frequency divider, seven-segment digital display module, light-emitting diode display module, and key switch module. Functions of each module: Elevator status control module, which is the core of the entire system design, completes the elevator status control; display module, which mainly displays system information and judges whether the elevator is running normally; frequency divider module, which divides the original 4MHz frequency to obtain the frequency required by the system; key switch module, which eliminates the misoperation and anti-jitter caused by mechanical key input. [align=center] Figure 1 Structure diagram of elevator[/align] 2.2 Design of elevator status controller 2.2.1 Design idea (1) Design of elevator input and output ports. The input ports include: an asynchronous set port, used to return to the initial state when the system is abnormal; a request port for lifting and lowering outside the elevator, where the first floor does not need to have a descent request, the top floor does not need to have an ascend request, and the middle floors should have both ascend and descent request ports; a request port for stopping at each floor inside the elevator; a clock input port for driving the elevator's ascending, descending, opening and closing actions, and a button clock input port with a clock frequency much higher than that of the elevator. The response output ports include: a lift request signal response port, which outputs logic "1" after a request signal is received, and returns to logic "0" after being responded to; a response port for stopping at each floor inside the elevator; a port indicating the elevator's position outside the elevator; a state indicator port for the elevator's opening and closing; and a lift indicator port for the elevator. (2) The elevator controller is implemented through a state machine, treating each second of elevator waiting and opening and closing as an independent state. Since the elevator rises (falls) one floor every second, the state machine can be triggered by a unified clock with a period of 1 second. Therefore, the state machine has 10 states: "stopon1 (elevator stops on the 1st floor)", "dooropen (door open)", "doorclose (door closed)", "doorwait1 (door open, waiting for 1 second)", "doorwait2 (door open, waiting for 2 seconds)", "doorwait3 (door open, waiting for 3 seconds)", "doorwait3 (door open, waiting for 4 seconds)", "up (ascending)", "down (descending)", and "stop (stop)". The transition conditions between each state are determined by the design requirements. 2.2.2 Program Design In the design of the constructor, two processes are designed to cooperate with each other: a state machine process and a semaphore control process. Many judgment conditions in the state machine process are based on semaphore signals generated by the semaphore process, and the extinguishing of the semaphore in the semaphore process is controlled by the "up (ascending)" and "down (descending)" signals transmitted from the state machine process. In the state machine process, when the elevator is in the ascending state, the indicator lights determine whether the next state should continue ascending or stop. Similarly, in the descending state, the indicator lights determine whether the next state should continue descending or stop. The most complex decision-making process occurs in the stopped state, where the indicator lights determine whether the elevator should ascend, descend, or stop. In the indicator light control process, a dedicated high-frequency button clock is used, increasing button sensitivity. However, the clock frequency cannot be too high, otherwise the buttons will become overly sensitive. The illuminated indicator light (logic value '1') after a button press serves as the condition for the state machine process, while the up and down signals (logic '1') turn off the corresponding indicator light. 2.3 The display module design adopts a dynamic display mode, cyclically illuminating three seven-segment displays. With a scanning frequency higher than the persistence of vision (24Hz), it achieves the visual effect of illuminating three seven-segment displays simultaneously while illuminating a single display. The signals for floor ascent, descent, and floor stop are displayed using a seven-segment display. The elevator's ascent, descent, and stop signals are represented by 3-bit binary numbers. A seven-segment decoder decodes the 3-bit binary numbers output by the elevator state controller into the 7-bit binary numbers required for the seven-segment display input. The simplified truth table is shown in Table 2.3. The corresponding decoding program and multiplexer display program are omitted. 2.4 Frequency Divider Design The frequency divider divides the input 4MHz signal into a 1Hz signal, which is provided to the state machine as an input signal. Additionally, the frequency divider divides the signal to 4000Hz, which is used as a scanning signal for the dynamic display module and the button module. Three frequency dividers were designed according to the design requirements. 2.5 Input Port Design In the state machine design, considering the CPLD capacity and taking a three-story elevator as an example, eight button input terminals are defined. The following are the key parameters: (1) Asynchronous set button, (2) 1st floor up request button, (3) 2nd floor up request button, (4) 2nd floor down request button, (5) 3rd floor down request button, (6) 1st floor stop request button, (7) 2nd floor stop request button, and (8) 3rd floor stop request button. 3 Design Results and Analysis 3.1 Synplify Synthesis of Elevator State Controller Synplify pro was used to synthesize the state change control program of the finite state machine written in VHDL language. The circuit schematic of the "RTL" (Register Transfer Level) mode after synthesis is shown in Figure 2. [align=center] Figure 2 Synplify pro Synthesis of State Transition Diagram[/align] 3.2 Simulation After the synthesis and compilation are completed, the reset signal is active high and set to 0. The liftclk clock signal is selected as 1HZ and the buttonclk clock signal is selected as 4000HZ. With appropriate input signals configured, the simulation results are shown in Figure 3. The elevator was initially stopped on the first floor. A request to descend from the third floor was received, so the elevator ascended to the third floor. After a passenger entered the elevator, they requested to descend one floor. At this point, a request to descend from the second floor was received, followed by a request to ascend. The elevator first stopped on the second floor, then descended to the first floor, and then responded to the second floor's request to ascend, ascending to the second floor. After a passenger entered the elevator, they requested to ascend to the third floor. Therefore, the elevator finally stopped on the third floor. [align=center] Figure 3 Simulation waveform of the three-floor elevator [/align] 3.3 Experimental Results In the complete system design, Max+Plus II was used to complete the hierarchical design of VHDL description and schematic diagram. In the low-level design, the function of each module was implemented using VHDL, and each module generated a device symbol that could be called by Max+Plus II. These device symbols were then connected together to form the entire system schematic diagram, as shown in Figure 4. [align=center] Figure 4 System circuit schematic diagram [/align] After the entire system design was completed, a .pof file was generated after compilation. After successful simulation, it was downloaded to the EPM7128SLC84-15 chip. The existing hardware circuit was connected according to the pin assignment diagram, and the experimental circuit is shown in Figure 5. [align=center] Figure 5 Experimental Circuit Diagram[/align] 3.4 Results Analysis Through actual hardware testing, the digital tube correctly displayed the floor, and the LEDs responded to display the elevator's status. Through testing different initial states, it was found that, except for some misoperations caused by button bounce, the elevator's state transitions completely conformed to the elevator's operating rules. This indicates that this design method is effective. Since it is easy to change the control function of the CPLD device through programming, and the basic state transition law of elevator operation does not change with the number of floors, it is only necessary to change the corresponding input and output port design to meet the design requirements of different number of floors. 4 Conclusion This design is based on a top-down design method, and the program control of the elevator's state transitions was implemented using VHDL. In the Max+Plus II environment, by using the unique synthesis function of Synplify Pro software, the compilation and simulation of the software program and the functional implementation of the programmable logic chip were optimized, greatly improving the design efficiency. This method can be widely used in the design of various complex state machine controls. References [1] Peng Bao, Fan Tingting, Ma Jianguo. FPGA design based on Verilog HDL language. Microcomputer Information. Vol. 20, No. 10, 2004, p81-82. [2] Li Zongbo, Wang Ronghui. VHDL design representation and synthesis. Beijing: Machinery Industry Press, 2002. [3] Pan Song, Huang Jiye. EDA technology application tutorial. Beijing: Science Press, 2002. [4] Chu Zhenyong, Weng Muyun. FPGA design and application. Xi'an: Xi'an University of Electronic Science and Technology Press, 2002.