Abstract: This paper introduces the characteristics and working principle of SDRAM, and proposes an FPGA-based SDRAM controller design method. The controller design, implemented using Verilog language, allows for convenient operation of the SDRAM. The controller has been successfully applied to the extended cache of high-capacity data loggers. Keywords: FPGA; SDRAM; Verilog; 1 Introduction In the development of high-speed data loggers, the inherent seek latency of hard disks prevents real-time writing of external data. Solid-state drives (SSDs) are relatively expensive, so a large-capacity external data cache is considered in the design. Among various random access memory (RAM) devices, SRAM is inexpensive and simple to design, but its capacity is generally small; DDR is fast and has large capacity, but its hardware and software design are relatively complex. SDRAM has the advantages of low price, small size, high speed, and large capacity, making it an ideal device to meet the bandwidth requirements of high-speed data recording designs. However, compared with SRAM, SDRAM's control logic is complex, and its interface differs significantly from ordinary memory. To resolve this contradiction, a dedicated SDRAM controller needs to be designed. This paper proposes an FPGA design for an SDRAM controller, using a state machine approach internally within the FPGA. The design uses Altera's Cyclone II series EP2C35F484C8N as the main control chip. The system clock is 75MHz. 2. Introduction to the working principle of SDRAM The SDRAM chip used in this design is Winbond's W982516, 4M×4BANKS×16BIT, two chips are connected in parallel to form a 32-bit data bus, and the burst read and write speed can reach 300Mbytes/s. The W982516 adopts a 54-pin TSOP package, the working voltage is 3.3V, and adopts a synchronous interface method (all signals are triggered by the rising edge of the clock signal) to run synchronously with the system clock. The W982516 has 13 row addresses and 9 column addresses. Like various SDRAMs, this SDRAM has the following characteristics: (1) It adopts the principle of row and column address reuse. The address lines of SDRAM provide different addresses under different commands, and the row and column addresses reuse 13 address lines. (2) It needs to be refreshed periodically. (3) When reading and writing, the row needs to be activated first. When reading and writing pages, the closed rows must be pre-charged before the new rows are activated for reading and writing. (4) Configure the mode register before the SDRAM is working normally. The SDRAM has a lot of control commands, see Table 1 for details. [align=center] Table 1 SDRAM Commands[/align] The Verilog code corresponding to the parsed commands is as follows: always @ (cmd) begin case (cmd) modeset:begin nCS<=1'b0; nRAS<=1'b0; nCAS<=1'b0; nWE<=1'b0;end refr: begin nCS<=1'b0; nRAS<=1'b0; nCAS<=1'b0; nWE<=1'b1;end prech: begin nCS<=1'b0; nRAS<=1'b0; nCAS<=1'b1; nWE<=1'b0;end actv: begin nCS<=1'b0; nRAS<=1'b0; nCAS<=1'b1; nWE<=1'b1;end wrt : begin nCS<=1'b0; nRAS<=1'b1; nCAS<=1'b0; nWE<=1'b0;end read: begin nCS<=1'b0; nRAS<=1'b1; nCAS<=1'b0; nWE<=1'b1;end nop : begin nCS<=1'b1; nRAS<=1'b1; nCAS<=1'b1; nWE<=1'b1;end endcase end 3 SDRAM Controller Design 3.1 System Design Block Diagram [align=center] Figure 1 System Design Block Diagram[/align] As shown in Figure 1, two W982516 chips are connected in parallel to form a 32-bit data bus SDRAM. The external data bus is 32-bit. FIFO1 is the first-level buffer for external data. When the data in FIFO1 exceeds 512 (the amount of data in one page of SDRAM), the SDRAM controller reads the data from FIFO1 and writes it to the W982516 for temporary storage. When the remaining space in FIFO2 is greater than 512, the SDRAM controller reads one page of data from the W982516 and writes it to FIFO2. The hard disk controller then writes the data in FIFO2 to the hard disk. 3.2 SDRAM Controller Design 3.2.1 Reset Initialization [align=center] Figure 2 SDRAM Controller Design Block Diagram [/align] As shown in Figure 2, the dashed box represents the initialization process. 200µs after power-on, an initialization operation configures the SDRAM's operating mode. Within 200µs, only NOP commands can be sent to the SDRAM. The initialization process is completed by starting the following instruction stream: first, a precharge all BANK instruction precharges all BANKs; then, eight cycles of automatic refresh instructions; and finally, the SDRAM's internal mode setting register is configured under the mode configuration instruction. The mode register specifies detailed information such as burst length, burst type, and CAS latency. For ease of flexible application, the SDRAM mode register is set to 0x027 in this design (burst length is a full page, CAS latency is 2). The SDRAM can only function properly after successful initialization. 3.3.2 Refresh Count Module The SDRAM requires refreshing 4096 rows within 64ms, which is one row refreshed every 15.6us. Since the system clock cycle is 13ns, the refresh count module needs to issue a refresh command to the SDRAM when it reaches 1170. As shown in Figure 3, when the refresh count module reaches 1170 or more, the comparator output rises to the D flip-flop, which outputs a high level to send a refresh request. After receiving the refresh request, the SDRAM controller executes the refresh command. After completing the refresh command, the SDRAM controller sends a refresh acknowledge signal to clear the output of the D flip-flop and simultaneously clears the refresh counter and starts counting again. [align=center]Figure 3 Refresh Module[/align] 3.3.3 Working Process After the FPGA completes the initialization of the SDRAM chip, it enters the idle state and then performs corresponding actions according to external signals, such as automatic refresh, reading and writing data. If an automatic refresh request is received, the controller sends an automatic refresh command to the SDRAM, with automatic refresh having the highest priority; if the data in FIFO1 exceeds 512 (as shown in Figure 1), the row to be written is activated first, and then the data is written to the SDRAM. Finally, after precharging, the row is closed and the system returns to the idle state. A register is used to record the number of rows of valid data in the SDRAM. At this time, the number of rows of valid data is incremented by 1, and the row address is incremented by 1. The write operation has the second highest priority; if the remaining space in FIFO2 exceeds 512 and the number of rows of valid data is greater than 0, a read operation can be performed. Similar to the write operation, the row to be read must be activated first, and then the data is read from the SDRAM and written to FIFO2. After precharging, the row is closed and the system returns to the idle state. At the same time, the number of rows of valid data is decremented by 1, and the row address is incremented by 1. The read operation has the lowest priority. This results in a 64Mbytes large-capacity circular buffer. The state transition code for the state machine during idle is as follows: `work_idle: begin if (refresh) // Received refresh request, highest priority work_state <= work_refresh; else if (ff_halffull) // FIFO1 buffer is half full, write to SDRAM first work_state <= work_write; else if ((wr_counter>0)&ff_halfempt) // FIFO2 buffer is half empty, read from SDRAM work_state <= work_read; else work_state <= work_idle; end` 4. Summary This design has been successfully applied to a certain type of radar, capable of recording real-time radar signals greater than 40Mbytes/s. The SDRAM controller operates stably, thus achieving the design goals of low cost, large capacity, and high speed.