Abstract: This paper introduces the characteristics of grating-stroke signals, proposes a hardware architecture design scheme of TMS320DM642 DSP + XC2S100E FPGA, analyzes the key technologies of buffer allocation in the conversion system, elaborates on the FPGA design scheme of the system's auxiliary processing device based on the introduction of the system's working principle, and presents the software flow of the core processing device DSP. Practice has proven the feasibility and reliability of the system. Keywords: raster-stroke; video; DSP; FPGA [b][align=center]Design and implementation of raster-stroke to LCD conversion system Luan Chun-Xu , Chen Xiao-Chuan, Yi Xiao-Qing[/align][/b] Abstract: The characteristic of raster-stroke signal is described. The hardware design proposal based on TMS320-DM642 DSP + XC2S100E FPGA is proposed. The key techniques about cache allocation of conversion system are discussed. After the operation principle of the conversion system is described, the design proposal of the subsidiary devices FPGA is elaborated and the software flow of the key devices DSP is presented. The practice shows that the system has feasibility and reliability. Key words: Raster-Stroke; Video; DSP; FPGA 0 Introduction Raster-stroke video signals have been widely used in modern military and civilian airborne electronic equipment[3]. The raster-stroke video signal is superimposed in space. The stroke scans out the character image, and then the raster scans out the image. The two are displayed in the same field of view[4]. The number of bus lines is 5, including X (X direction scanning signal), Y (Y direction scanning signal), Z (stroke on/off signal), V (raster on/off signal), M (video gate signal, segmentation mark of raster and stroke). The raster video signal is composed of X, Y, and V, and the stroke video signal is composed of X, Y, and Z. There is a strict synchronization relationship between these five signals. Zhu Jun et al. have implemented a stroke to raster conversion system using a complex CPLD. However, due to the fast change rate of the input analog signal and the superimposed noise, if only a simple system conversion is performed, image blurring, creeping, character distortion and other phenomena will occur. Therefore, we designed a conversion system based on TMS320DM642 DSP. This system has been successfully applied to airborne equipment and has better clarity and better anti-interference ability. 1 System Structure and Working Principle 1.1 System Structure Design This system mainly realizes the conversion and optimized display function of 48FPS (frames per second) mixed video signal to 60FPS LCD digital signal. The system principle block diagram is shown in Figure 1. The system mainly uses chips such as the TMS320 DM642 DSP produced by TI, the XC2S100E FPGA produced by Xilinx, and the LTC1420 A/D chip produced by Linear Technology. The TMS320 DM642 DSP is a high-performance fixed-point DSP chip for video/image processing launched by TI in 2003. It has an instruction execution speed of up to 5760 MIPS, eight high-performance independent functional units, and a 64-bit EMIF that can support 1024MByte space. It seamlessly connects to asynchronous SRAM and EPROM, and synchronous SDRAM and SBSRAM. Furthermore, data exchange between memories and between memories and peripherals can be completed quickly through EDMA. The XC2S100E FPGA is a Xilinx Spartan II series product, supporting processing speeds up to 200MHz, with 202 I/Os, 38,400-bit distributed RAM, and 40K-bit block RAM. The LTC1420 is a 10Msps, 12-bit A/D converter chip. The MT48LC4M32B2 is a 4M 32-bit chip, supporting speeds up to 166MHz. The Am29LV160D is a 2M x 8-bit chip with a maximum access speed of 70ns. [align=center] Figure 1 System Principle Block Diagram[/align] 1.2 System Working Principle 1.2.1 System Buffer Design This video signal conversion system is a real-time system, and buffer allocation is a key part of the system design. Buffering serves two main purposes: firstly, to improve data bus utilization, and secondly, to reduce the impact of the speed difference between the CPU and external memory. The system mainly uses double buffering and quad buffering. The double buffer operates in a ping-pong manner, with one buffer serving as the read buffer and the other as the write buffer at any given time. The quad buffer operates in a cyclic manner, with buffer reads proceeding sequentially from A to D, and buffer writes also proceeding sequentially from A to D. Buffer data updates are determined by a flag; once buffered data is read, the buffer switches to write mode to refresh its data. The system buffer structure is shown in Figure 2. Functionally, the system mainly includes four types of buffers. The first type is the video data sampling buffer, primarily including the AD_FIFO in the FPGA and the video sampling processing double buffers A and B in the DSP. The FIFO in the FPGA buffers the video signal after A/D sampling. Adding a FIFO between A/D sampling and the DSP reduces the DSP data bus load, enables batch data transmission, and improves DSP data throughput. The sampling double buffer in the DSP is a soft buffer; the double buffering function is alternately controlled by a flag. When one buffer receives FPGA data, the other buffer is being read by the video processing module. The use of sampling double buffers avoids write and read conflicts, enabling real-time processing of sampled data. The second type is the video image forming double buffer A and B. After the sampled raw video signal is processed by filtering, it is sent to the internal digital image forming buffer. Each of these two buffers stores a digital image. Using double buffers can complete video data reconstruction, realize scan conversion, and prevent data read/write conflicts. These two buffers also operate in a ping-pong mode, where one buffer is forming image data while the other is sending image data to SDRAM. The third type is the video image transmission buffer, which stores the converted video data. Due to the rate difference between the input 48FPS and the output 60FPS, that is, the SDRAM read rate is greater than the write rate, the SDRAM quad buffer used in the system can prevent this speed difference read/write conflict and realize the conversion from slow frame rate to fast frame rate. The fourth type is the LCD output display buffer. The LCD FIFO is a hard buffer for the digital video signal output. Setting up the LCD FIFO between SDRAM and LCD is mainly to reduce the impact of the speed difference between them. [align=center]Figure 2 Buffer Structure Diagram[/align] 1.2.2 System Working Principle The four analog signals X, Y, Z, and V first pass through the AD813 conditioning circuit and are then input differentially to the LTC 1420 A/D conversion chip. This chip samples the analog video signals and converts them into digital video signals. The sampled digital video signal, along with the M signal, forms a 32-bit video signal, which is then sent to the FPGA for decoding, filtering, and synchronization before being buffered in the FPGA AD FIFO. When the FIFO is half-full, it sends a half-full signal to the DSP, triggering an EDMA event. The EDMA reads the EDMA frame containing 200 data points from the FIFO and stores it in the write buffer of the DSP A/D double buffer. The DSP reads the video signal from the DSP A/D buffer, performs filtering and other processing, and stores the processed data in the digital image forming buffer to reassemble the video image data. Once the entire image data is formed, an EDMA event is triggered, and the digital image data is split and sent to the external SDRAM write buffer via EDMA. When the FPGA LCD FIFO is half empty, an EDMA event is triggered, sending buffered data in SDRAM in 100-data-per-frame EDMA chunks to the LCD FIFO. The buffered data in the LCD FIFO is then sent to the LCD controller for final display on the LCD. 2. FPGA Design The FPGA design uses the ISE development platform, a Xilinx CPLD/FPGA development platform. This platform integrates over a dozen auxiliary design software programs and supports schematic, VHDL, and VerilogHDL input. Logic design, final configuration file generation, and FPGA loading can all be completed on this platform. During development, the free IP cores and logic simulation software provided by ISE accelerated the schematic logic design process. During debugging, the ChipScope Pro online logic analyzer facilitated system debugging and shortened the system development cycle. The system FPGA block diagram is shown in Figure 3. The FPGA plays a role in auxiliary video signal processing in this system, serving as the link between the external video signal interface and the DSP. Its functional modules mainly include an FIR filter, input video signal decoder, A/D FIFO, LCD FIFO, output video signal decoder, and LCD control circuit. [align=center]Figure 3 FPGA Principle Block Diagram[/align] The X, Y, V, Z, and M inputs on the left side of Figure 3 are digital video signals output from the A/D converter. After X and Y enter the FPGA, they are converted into coordinate points of the digital image through an FIR low-pass filter and decoder. To ensure the synchronization of the five signals X, Y, Z, V, and M, the Z, V, and M signals need to be delayed by a delay circuit. The transformed and delayed signals are combined into 32-bit data and stored in the AD FIFO. When the FIFO is half full, the AD FIFO generates a FIFO half-full event to the DM642. The LCD FIFO on the right side of Figure 3 mainly buffers the output video stream. The video data in the buffer is decoded by the output video signal and output to the LCD synchronously with the HS, VS, DE, and CLK generated by the LCD timing generation circuit. 3 System Software Design The DM642 software mainly consists of an application program and a DSP/BIOS embedded operating system. It mainly completes functions such as FPGA configuration, video image filtering, image matrix formation, and inter-peripheral coordination. The DM642 main program flowchart is shown in Figure 4. The system program and FPGA configuration files are stored in FLASH. After power-on, the DSP loads the system program from FLASH and configures the FPGA. After initializing all peripherals and buffers, the A/D and LCD drivers are enabled, and the system begins to operate collaboratively. [align=center] Figure 4 System Main Program Flowchart[/align] Data transmission in the system does not require DSP participation and is completed independently by EDMA. EDMA completes three parts of data transmission: from the A/D FIFO to the DSP's internal A/D double buffer (denoted as AD_EDMA), from the internal digital image double buffer to the SDRAM quad buffer (denoted as SDRAM_EDMA), and from the SDRAM quad buffer to the LCD FIFO (denoted as LCD_EDMA), and generates EDMA interrupts for each part. The EDMA interrupt handler flowchart is shown in Figure 5. In the EDMA interrupt handler, the various types of EDMA interrupts are first judged according to the EDMA channel identifier. If the interrupt is AD_EDMA, the A/D dual buffer is switched and an AD soft interrupt is triggered. The AD soft interrupt program mainly distinguishes the newly written A/D sampling data, that is, it determines which are stroke signals and which are raster signals. If the interrupt is SDRAM_EDMA, an SDRAM soft interrupt is triggered. If the interrupt is LCD_EDMA, the LCD_EDMA source address is changed. The flowchart of the SDRAM soft interrupt program is shown in Figure 5. In the SDRAM soft interrupt, it first determines whether a frame of image has been transmitted. If the transmission is complete, it switches the DSP to send to the fourth buffer of SDRAM, that is, changes the destination buffer address of SDRAM_EDMA; otherwise, it continues to send the previous frame of image. The flowchart of the A/D processing task program is shown in Figure 5. In the processing task, it first checks whether the data in the A/D sampling buffer is a raster signal or a stroke signal. If it is a stroke signal, it performs special digital filtering processing and converts it into a digital image and adds it to the digital image matrix; if it is a raster signal, it directly fills the digital image matrix. After processing, SDRAM_EDMA is triggered to send the prepared image data to SDRAM; if it is not ready, it is not sent. [align=center] Figure 5 System Subroutine Flowchart[/align] 4 System Verification After on-site debugging, the system can correctly display the test image without jitter or creep. Furthermore, when artificial scrambling is applied to the input signal, it has no significant impact on the system's display, meeting the design requirements and engineering applications. Conclusion This article designs and implements a video signal conversion system based on the DM642. The system's working principle and FPGA design scheme are explained in detail. Practice has proven that the image display is correct, stable, clear, and less susceptible to noise interference, meeting engineering applications. The implementation of this system has certain reference value for applications in the field of video conversion. References: [1] Chen Qinghua, Xie Xiaofang, Gao Bo. Design and implementation of multi-functional display simulator [J]. Firepower and Command Control, Vol. 32, No. 8, August 2007, pp. 110-112. [2] Lai Yueshen, Shang Yaceng, Song Fanglin, Liu Fang, Chen Xiao. Realization of raster-stroke compatible scanning by chasing method [J]. Electronic Technology Application, No. 11, 2005, pp. 55-57. [3] Zhu Jun, Lin Zulun, Zhang Yide, Yang Jianjun. Research on random scan to raster scan conversion system [J]. Journal of University of Electronic Science and Technology of China, Vol. 34, No. 6, December 2005, pp. 783-785. [4] TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J–JULY 2002–REVISED [Z] AUGUST 2005, http://www.t i.com . [5] TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide Literature Number: SPRU266E February[Z] 2006, http://www.ti.com . [6] Spartan-IIE 1.8V FPGA Family: Complete Data SheetDS077[Z] July 28, 2004, http://www.xilinx.com .