Abstract: This paper analyzes the interface of a high-speed camera and proposes a high-speed CCD image acquisition and storage scheme based on the PCI bus. This scheme first utilizes an FPGA to preprocess CCD image data to ensure data synchronization and bit depth matching; then, it acquires data via a PCI9054; finally, the data is piped and stored in a SCSI hard disk array. System test results show that this scheme constructs a high-speed image acquisition system with strong real-time performance and convenient operation. Keywords: high-speed camera, FPGA, PCI bus, hard disk array[b][align=center] High-speed CCD Image Storage System Design Based on PCI Bus Cao-Qi, Bi Du-yan, Wang Hong-xun[/align][/b] Abstract: By analyzing the interface of high-speed camera, a scheme collecting high-speed CCD image based on PCI bus was addressed. First of all, to guarantee the synchronization of data and the match of bits number, the scheme utilized FPGA to preprocess the data of CCD image. Then, PCI9054 collected the image data .At last, SCSI Hard Disk Array stored the image data by way of the pipeline fashion. The test result the scheme constructed high performance and easily manipulated real-time system on high-speed image collection. Keyword: High-speed camera, FPGA, PCI Bus, Hard Disk Array 1 Introduction Reconnaissance and surveillance play an important role in military struggle. Among various reconnaissance/surveillance technologies, aerial reconnaissance holds a crucial position, visible light reconnaissance is an important form of reconnaissance, and unmanned reconnaissance aircraft have shown broad development prospects. The development of modern science and technology has brought new opportunities for the development of modern aerial reconnaissance and surveillance technologies. A major approach to aerial reconnaissance is to use high-performance, high-speed cameras to take aerial photographs and collect various image information. However, the high resolution and large amount of information in digitized reconnaissance images make subsequent processing, transmission, and storage extremely difficult, thus posing a significant challenge to the design and implementation of airborne image/video systems. To address these issues, this paper, based on a certain type of high-speed camera, utilizes a low-cost FPGA to construct a high-performance image acquisition and storage system, enabling the acquisition and storage of high-resolution, high-frame-rate reconnaissance images. 2. Introduction to a Certain Type of High-Speed ​​Camera The high-speed camera selected for the system is a high-resolution, high-speed line-scan digital camera. Its image sensor employs an advanced CCD (Charge-Coupled Device) image sensor and utilizes world-leading high-sensitivity scanning imaging technology—high-speed TDI (Time Delay and Integration) technology, multiple exposure technology, and enhanced blue response. This allows the camera to provide better sensitivity characteristics than single-output line-scan cameras, with a total data transfer rate of up to 200MB/s. The camera interface mainly includes six interfaces on the rear panel: four are data output interfaces, each including a 16-bit data signal, a 1-bit data synchronization signal, and a 1-bit synchronization clock signal, with the signal level output format being LVDS level format; the other two interfaces are the control signal interface and the power interface, respectively. Under the action of the control signal, the camera synchronously outputs 8×8-bit standard grayscale image data, including the synchronization clock signal (STROBE) and the horizontal synchronization signal (LVAL). The image resolution can be selected as 4096×3072 (the resolution used in this system) and 2048×3072. In the camera control interface signals, the line trigger signal (EXSYNC) is crucial. It is responsible for triggering the output of image data; the rising edge of the line trigger signal triggers the data and indicates that the data is valid. Camera triggering requires a falling edge for this signal, with a minimum trigger frequency of 300Hz. 3. System Hardware Design and Working Principle The hardware system of this design mainly includes three parts: level conversion, data reception and preprocessing, and data acquisition and storage. Figure 1 shows the system hardware block diagram. In terms of bus structure, the system adopts a PCI bus structure that meets high-speed data transmission requirements. The PCI9054 is a 32-bit, 33MHz PCI bus master I/O accelerator launched by PLX Corporation. It employs various advanced technologies, making the complex PCI interface application design relatively simple. Considering resources and cost, the FPGA selected is Altera's low-cost Cyclone series chip - EP1C6Q240C8. The storage medium is a SCSI disk array, which can meet the requirements of high-speed, large-data-volume storage. [align=center] Figure 1 System principle block diagram[/align] System working principle: When the system is powered on, a series of initialization tasks are completed: the PC configures the registers of the PCI9054 through the underlying driver to put it into normal working mode (C mode) [2]; the FPGA is powered on and the user circuit is configured (at this time, the internal logic of the FPGA and the PCI9054 are in a waiting state). After the PC application starts, it sends a data transmission instruction to the PCI9054. The PCI9054 receives the data transmission instruction and notifies the FPGA to start working through the LOCAL BUS: the FPGA generates a line trigger signal (EXSYNC) to trigger the camera to take pictures and transmit data. Then, the PCI9054 enters the working state, starts to collect data, and stores the data in the disk array. The internal logic of the FPGA and the PC application judge that a frame of image transmission is completed by line counting and enter the waiting state one after another. However, after the PC application receives a frame of image and enters the waiting state, it will continue for a certain period of time and automatically trigger the next data transmission instruction to notify the FPGA to start the next frame of image transmission. The PCI9054 chip's level format is 3.3V LVTTL, and the camera output signal's level format is LVDS. Based on the overall system requirements, it is necessary to convert the LVDS camera output signal to LVTTL before image preprocessing. Data reception and preprocessing: The FPGA completes the image preprocessing function. The FPGA is a chip dominated by parallel operation, and its processing speed is faster. The data preprocessing process includes: data buffering and bit-to-bit conversion. Data buffer [3]: The camera uses four channels to output image data. The data transmission of each port is referenced by the clock of this port. During the transmission process, due to various differences such as the different lengths of the transmission cables, the clock signals of each port will have relative phase drift, so that the data output of the four ports is not completely synchronized, which is not conducive to the synchronous acquisition of image data. In order to eliminate data asynchrony, the FPGA is designed with a data buffer group composed of four FIFOs. The effective data width of each port is 16 bits. It takes 512 clock cycles to transmit a line of 4096 data. Therefore, the FIFO depth is set to 512 words. The camera sends four LVAL signals as write enable signals for their respective channels, and four STROBE signals as write clocks for their corresponding channels. The FIFO output uses the system clock (15MHz) as a unified data synchronization clock and includes a read request signal. When the FIFO is half-full, data is read, and the buffered data is output in a 64-bit width format synchronized with the system clock. Bit-to-parallel conversion: The PCI9054 chip's LOCAL terminal offers two effective data bit width options: 8 bits and 32 bits (the 9054 register settings can be changed; this system uses 32 bits to ensure data acquisition speed). However, the camera's output data, after buffering, remains 64 bits. To meet the PCI9054's data acquisition bit width requirements, the 64-bit data must be bit-to-parallel converted to 32-bit transmission. This system design internally in the FPGA sends the high 32 bits and low 32 bits of the data to the input of a 2-to-1 BUSMUX multiplexer, with the system clock level selecting the data output. While 64-bit data is converted to 32-bit data transmission, the data rate doubles (30M/s). For the entire system, the continuous storage speed of the storage system is a crucial parameter. Data acquisition and storage utilizes a microcomputer as the main body, with a SCSI interface card and a 9054 interface card connected to its PCI bus. The 9054 interface card is used for data acquisition, and two SCSI hard drives are connected to the SCSI interface card, forming a RAID-0 hard drive array, which can greatly improve the continuous storage speed of the hard drives. When using the PCI9054 for data acquisition, the data transmission path is: PCI bus - memory - hard drive array. Two transmission schemes are available: the first is single-line acquisition and storage, which obviously reduces the data acquisition speed. This system chooses the second scheme: pipelined storage, as shown in Figure 2. Theoretically, the data acquisition speed of pipelined storage should be twice that of single-line acquisition. [align=center] Figure 2 Pipeline Storage Timing Diagram[/align] 4. Partial Software and Hardware Program Design PCI9054 Local Bus Hardware Driver The PCI9054 local bus is the bridge for communication between the peripheral (FPGA) and the 9054. Acquiring 9054 image data requires that the 9054 local bus signals meet certain timing requirements to ensure synchronous data transmission, which requires FPGA-side hardware driving. The driver is a state machine written in Verilog HDL code, as shown below [2][4]: always @ (posedge CLK) begin casex (CurrentState) 1'b0: begin if (!LLADS_) begin LLREADY <= 1; CurrentState <= 1; end else begin LLREADY <= 0; end end 1'b1: begin if (LLBLAST_) //burst loop repeat begin LLREADY <= 1; CurrentState <= 1; end else //last loop begin LLREADY <= 0; CurrentState <= 0; end end default: CurrentState <= 0; Endcase end assign LLREADY_ = (LLREADY) ? 1'b0 : 1'b1; 4.2 PCI9054 Driver Layer and Application Layer Design The PCI acquisition card used in the system is not Windows standard hardware, and the driver needs to be developed by ourselves. WDM programming is used here. Dual-thread operation is adopted to improve speed. Since writing to the disk is slow, it would be inefficient to wait until the disk is written before reading the local bus. Therefore, a dual-thread, dual-buffer read and write operation is started [5]. Partial program code: BOOL GetData() { ... // Create a waiting thread for driver interrupt and a file writing thread hEvent_Disk=GreateEvent(NULL,TRUE,TRUE,NULL); hEvent_Mem = CreateEvent(NULL,TRUE,FALSE,NULL); _beginthread(WaitForDataThread,0,NULL); _beginthread(WriteDiskThread,0,NULL); // Start DMA transfer SetDma(); BlockDmaLocalToPci(dmabuffer, BLOCK_ONE_DMA); } void WaitForDataThread(void * pParam) {} void WriteDiskThread(void * pParam) {} 4.3 Data transfer instruction generation The PC application generates data transfer instructions to trigger data transfer. The instruction is generated through the low-level driver of the 9054 on the PC side, setting the level of the USERO pin on the 9054's LOCAL side, enabling the FPGA to enter the working state, and generating a camera line trigger signal (EXSYNC) to trigger the camera to take pictures and transmit data. When the USERO signal is high, both the FPGA and the 9054 are in a waiting state; the falling edge of USERO triggers data transmission, enabling the FPGA and the 9054 to enter the working state; after data transmission is completed, USERO is pulled high. The timing is shown in Figure 3. [align=center] Figure 3 Data Transmission Protocol[/align] 5 System Testing and Engineering Considerations The microcomputer environment for this system test is as follows: CPU, Pentium(R) 4, 2.40GHz; Memory, 333MHz, 512MB/s; Northbridge chip, 845PE; Operating system, Windows Server 2003; SCSI hard disk space, 120G. System test results: The stable single-line image storage rate is 37.2 MB/s, the stable pipeline storage rate is 71.2 MB/s; the continuous recording time is 25 minutes. Engineering Considerations: System speed is primarily limited by two bottlenecks: the hard drive itself and the PCI bus. Although this system utilizes a high-speed hard drive, operational efficiency remains an issue. Data transfer from the FPGA to the PCI9054 uses a standard hard drive cable, whose upper frequency limit is 33MHz, restricting data acquisition speed. Simultaneously, since the system needs to transfer data via the PCI bus, and computer PCI buses are typically 32-bit, 33MHz buses with a theoretical data transfer rate of 132MB/s, the actual measured sustained transfer rate is below 100MB/s when only one device is connected. When a disk adapter is added, the data transfer rate drops even further. System stability depends mainly on the fault tolerance of the FPGA's internal logic and the stability of the microcomputer. In a high-speed storage environment, the microcomputer system is prone to crashing; therefore, the highly stable Windows Server 2003 operating system was chosen as the storage environment for image acquisition. The author's innovation lies in utilizing FPGA and PCI9054 to achieve high-speed, high-resolution image acquisition and storage. References: 1. High-Speed ​​TDI Line Scan Camera-Camera User's Manual. America: Dalsa, 2002. 2. PCI 9054 Data Book. America: PLX Technology, 2000. 3. Wang Hongxun et al., Acquisition and Buffering of High-Speed ​​Reconnaissance Image Data. Microelectronics & Computer [J]. 2004, 10-1. 4. Du Jianguo, Verilog HDL Hardware Description Language [M]. Beijing: National Defense Industry Press, 2004. 5. Pei Xilong, Design and Implementation of High-Speed ​​Data Acquisition Card System Based on PCI Bus. Microcomputer Information [J], 2006, 7-1: 129-131.