1. Introduction In low DC output voltage isolated switching power supplies (SMPS) with the main PWM controller located on the primary side, specially designed MOSFETs are typically used as synchronous rectifiers (SRs). MOSFETs used as SRs have very low conduction losses, contributing to improved system efficiency. In primary-side controlled isolated SMPS topologies, generating a suitable SR control signal is difficult because there is no PWM control signal on the secondary side of the isolation transformer. However, relevant data can be obtained from the transformer secondary output. Due to the presence of parasitic elements in the circuit, the synchronization signal is delayed relative to the primary PWM signal when withdrawn from the isolation transformer output, and oscillations occur in discontinuous conduction mode (DCM). Therefore, the control circuit driving the SR must be able to avoid erroneous operation. In primary-side controlled isolated topologies, appropriate control circuitry is needed to drive the SR to handle the timing issues of the synchronous clock signal being withdrawn from the isolation transformer output and the timing of the drive signal relative to the clock input. Improper SR control can lead to "crossconduction" between the two devices. Meanwhile, in the secondary side of the isolated topology, due to the delay relative to the primary main switch (MOSFET) drive signal, a short circuit will form between related components, resulting in a "shootthrough" phenomenon. The mechanism of shootthrough depends specifically on the converter topology. 2 Digital Control Method for Synchronous Rectifiers Among the schemes used to generate SR drive signals, the digital control method is preferred. 2.1 Basic System Structure The SR digital control system generally consists of an oscillator (OSC), a Finite States Machine (FSM), two coupled up/down (UP/DOWN) counters, and two control output logic units, as shown in Figure 1. [img=332,231]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/242.jpg[/img] The control circuit has 3 inputs and 2 outputs. Two outputs provide complementary drive signals to the two MOSFETs on the secondary side of the isolation converter. Three inputs include one clock signal and two output anticipation time settings. The two outputs, OUT1 and OUT2, do not overlap when on or off. A square wave signal with a switching frequency of fs appears at the clock input, and the anticipation timing is set via an external input. The two counters operate differently: the DOWN counter handles output cutoff, while the UP counter continuously acquires data during the OUT2 switching cycle or the OUT1 on-time. The control system preprocesses the output during the off-time of the switching cycle based on information stored in previous cycles. Using this control method, the switching cycle and on-time (tON) are continuously monitored cycle by cycle. 2.2 Stable Conditions Under steady-state conditions (fixed frequency and fixed duty cycle), the waveforms related to output OUT2 in two switching cycles are shown in Figure 2. [img=332,231]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/242.jpg[/img] During the first switching cycle (TS1), on the rising edge of the clock input, the first of the two (UP/DOWN) counters begins counting the internal clock (CK) pulse. On the rising edge of the next clock input (the end of TS1), the counter stops counting. The number of pulses counted (n2) takes into account the duration of the switching cycle. The stored data is used in the next switching cycle. During the second switching cycle, on the rising edge of the internal clock input, the first counter counts the internal clock pulses from largest to smallest, and terminates when it has counted (n2 - x2) pulses. The second counter counts new, yet-to-be-counted internal clock pulses and corrects the relevant data during the switching cycle (TS) as needed. The total advance cutoff value of OUT2 is X2·TI (TI is the internal clock pulse period), and it is set via the expected time input of OUT2. The function of the UP or DOWN counter in each cycle is swapped relative to the previous cycle. To expect OUT1 to turn off, the other two UP/DOWN counters will take into account the relevant data during the on-time (tON) period, and the relevant waveforms are shown in Figure 3. [align=center][img=332,230]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/243.jpg[/img] [img=341,256]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/244.jpg[/img][/align] During the first switching cycle, the first counter starts counting on the rising edge of the clock input and stops on the falling edge of the clock input. The number of pulses counted during this period is n1, only counting the pulses within the tON time period. During the second switching cycle, the first counter decrements, stopping when it counts n1 - x1. The total lead time for OUT1 is x1·Ti, set by the expected time input of OUT1. The second counter counts the number of pulses between the rising and falling edges of the clock input upwards (from smallest to largest). 2.3 Variation Conditions 2.3.1 Switching Frequency Changes When the switching frequency (fs) changes, there are three possible cases for output OUT2: 1) TS1>TS2 When the second switching period TS2 is less than the previous period TS1, the turn-off of OUT2 is delayed. It does not lead relative to the clock input, but is forced to turn off with the leading edge of the clock input. Figure 4 shows the relevant waveforms under this condition. 2) TS1>TS2 The turn-off waveform is shown in Figure 5. In this case, OUT2 turns off early. The conduction time of the MOSFET body diode is exactly one cycle, and the efficiency loss is very small. [img=307,193]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/245.jpg[/img] 3) TS1 When the on-time tON1 of the first switching cycle is greater than the on-time tON2 of the second switching cycle, the timing diagram of the clock input, internal clock, and output OUT1 waveforms is shown in Figure 7. In this case, the turn-off of OUT1 is delayed and not advanced relative to the clock input; it always turns off immediately on the falling edge of the clock input. 2) tON1 The above method determines the action of the next cycle by measuring the previous cycle, performing cycle-by-cycle control. The expected total number of internal clock pulses to turn off the synchronous rectifier MOSFET is X1 or X2. The higher the internal oscillator frequency (fi), the higher the expected time accuracy. [align=center][img=319,227]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/247.jpg[/img] [img=319,241]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/248.jpg[/img][/align] 3 STSRx Series Intelligent Driver ICs The STSRx series ICs are devices specifically designed by STMicroelectronics for driving synchronous rectifiers in isolated SMPS. The clock signal for these ICs is obtained from the secondary output of the isolation transformer, providing appropriate control signals to drive one or two MOSFETs used as SRs. 3.1 STSR2 The STSR2 is used to drive two synchronous rectifiers in a single-ended forward topology. This IC includes the control system described above, and incorporates two high-current N-channel MOSFET drivers and a clock buffer, among other unit circuits. The pin names and application circuits of STSR2 are shown in Figure 9. The pin functions of STSR2 are as follows: VCC power supply voltage, ranging from 4.5V to 5.5V; PWRGND and SGLGND are the reference terminals for power signals and control logic signals, respectively; CLOCK synchronization signal input; OUTGATE1/22 high-current complementary outputs. Due to the IC's own dead time, there is no overlap between two turn-on times; SETANT2 sets the expected off time for OUTGATE2 (four different expected times are available); [img=361,231]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/249.jpg[/img] INHIBIT enables OUTGATE2 when the input at this pin is higher than a very low threshold voltage. In forward converter applications, the on-time of OUTGATE2 is forced to be minimized. 3.2 STSR3 STSR3 is a control IC specifically designed to drive a SR in a flyback topology. Its pin names (symbols) and application circuit are shown in Figure 10. The main difference between STSR3 and STSR2 is that STSR3 has only one high-current gate drive input (OUTGATE). [img=360,245]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/2410.jpg[/img] 3.3 STSR4 STSR4 is a control IC specified for driving SRs in push-pull, half-bridge, or full-bridge dual-ended output topologies. A typical application circuit for this device is shown in Figure 11. STSR4 contains two high-current N-channel MOSFET driver outputs and two clock inputs (CLOCK1 and CLOCK2), receiving clock signals from the secondary winding of the isolation transformer. STSR2, STSR3, and STSR4, in different types of isolated topology applications, all obtain clock signals from the transformer's secondary output to generate appropriate gate drive signals for one or both MOSFETs used as SRs, completely solving all the problems that easily arise in SR control and effectively improving system stability and reliability. [img=340,226]http://www.cechinamag.com/images/Article/6eb68dc3-a7e9-4b7c-b4da-f8be78bcd61c/2411.jpg[/img] 4 Conclusion In isolated SMPS topologies, the digital control/drive technology used to drive SRs has many advantages over the so-called "self-driven synchronous rectification" method that requires additional magnetic reset technology. The digital control method uses a main PWM controller in a primary-side SMPS isolated topology to utilize data directly from the variable.