Abstract: Based on the expatching of relevant design requirements, this paper introduces the development process of a PCI bus-based analog high-speed CCD data output system for testing purposes, including the system's hardware design and related software development. The design concept and methodology are emphasized in detail. Keywords : PCI bus, PCI 9054, WinDriver [b][align=center ] High Speed ​​Data Outputting System Based on PCI Bus Pi Hai-feng Li Zi-tian Xu Xiu-zhen Xue Li-jun[/align][/b] Due to the massive amount of data, the data acquired by CCD imaging systems is usually compressed before storage. During the development of a spectral imager, a testing device is needed to simulate the CCD imaging system of a spectral imager, continuously outputting known data and time-series signals. By comparing the known transmitted data with the compressed received data, the performance indicators of the data compression system can be quantitatively tested. 0. System Requirements and Design Concept The high-speed data output card in this paper simulates the data output process of the spectral imager's CCD system. The data output format of the spectral imager's CCD system is as follows: [align=center] Figure 1 Data Output Format of the Spectral Imager's CCD System[/align] Image data and auxiliary data share a time-division multiplexing data line. In the forward frame, 256 (rows) x 512 (columns) x 12bit image data is transmitted, and in the reverse frame, 128 x 12bit auxiliary data is transmitted. One frame cycle contains 131200 x 12bit data, and a complete spectral image contains 512 frames of data. The system output clock is 8.9 MHz, and all output signals are LVDS level interfaces. To achieve the simulation effect, the data output card is required to continuously output data with the same data format and interface; simultaneously, to test the effectiveness of the compression algorithm used by the subsequent data compression system for image data with different characteristics, the data output card is also required to be able to easily change the output data. To meet these system requirements, a PCI bus-based design was chosen: the image data file to be output is placed in a specific memory area as the data source. Under computer control, the memory area containing the data file is read cyclically, and the read data is sent out. This achieves the effect of simulating CCD system data output. If the output data needs to be changed, the new data only needs to be placed back into the memory area, which has strong flexibility and makes the testing process simpler. 1. System Hardware Design The hardware structure block diagram of the high-speed data output card is shown in the figure below. The PCI bus device interface uses the dedicated interface chip PCI 9054. The system clock signal comes from the PCI clock provided by the computer and the card's own 8.9 MHz crystal oscillator. The timing control of the entire process is completed by a programmable logic device (PLD), which controls the generation of a timer interrupt for the PCI 9054. The PCI 9054 responds to this external interrupt and sends a PCI interrupt signal to the computer on the PCI bus. When the host computer detects this interrupt signal, it immediately controls the PCI 9054 to read data from the memory area specified by the host computer in continuous DMA mode and sends it to a large-capacity FIFO for data buffering. The 12-bit image data in the FIFO, along with the data clock and frame synchronization timing signals, are converted into differential signals by an LVDS driver and sent to subsequent devices for processing. [align=center] Figure 2 Hardware structure block diagram of the high-speed data output card[/align] In this system, the PCI 9054 is set to C working mode, i.e., 32-bit address, 32-bit data, and bus non-multiplexed working mode. Since the PCI 9054 sends all data read from the host computer to a single device, the local address lines are inactive, and only the high 12 bits of the data lines are used. In addition, this design uses a serial EEPROM 93LC56B to configure the PCI 9054. After power-on, the PCI 9054 automatically reads the data in the 93LC56B, sets the relevant registers, and completes the initialization operation. Given the high speed and large data volume characteristics of this system, commonly used FIFOs are insufficient. Therefore, a 384K x 8-bit video frame memory AL422B is selected as the data buffer. The AL422B consists of 3M bits of DRAM, with a maximum operating frequency of 50 MHz. It has independent input/output interfaces and read/write clocks, allowing simultaneous read and write operations. The four input signals /RE, /WR, /REST, and /WRST control the read, write, and read/write pointer reset operations of the AL422B, respectively. In this system, two AL422B chips are connected in parallel, expanding into a 384K x 16-bit FIFO memory. The timing control of the entire process is completed by the programmable logic device (CPLD). Its functions include: sending timer interrupt signals to the PCI 9054, which requests an interrupt from the host computer; controlling the read/write timing of the data buffer AL422B, including its initialization and reset operations; and generating the timing signals required by the PCI 9054. 2. System Software Development The software of the entire system includes the PCI 9054 driver and host computer application, the image data preprocessing (format conversion) program, and the VHLD program for the CPLD. Here, only a brief introduction to the development of the PCI 9054 driver and application is given. WinDriver is a development toolkit produced by Jungo, which supports bus architectures including PCI/CardBus/ISA/ISAPnP/EISA/CompactPCI and USB, greatly simplifying the process of generating hardware drivers and developing applications. WinDriver version 6.03 was used in this development. WinDriver has built-in drivers for various PCI/USB interface chips, including the PCI 9054. Therefore, simply insert the designed PCI card into the computer, run the WinDriver wizard, and select the corresponding PCI interface chip from the list. As long as the hardware interface is connected correctly, the corresponding .inf file will be generated. The .inf file contains information about the PCI hardware device, such as device type, manufacturer, model, and the path to copy the file. Windows can only locate the PCI card and install its driver through the .inf file. [align=center] Figure 3: Interface for generating PCI card hardware device information file (.inf file) using WinDriver[/align] The host computer software development adopts user mode, and its flowchart is shown in Figure 4: [align=center] Figure 4: Host computer software flowchart[/align] Since the AL422B does not provide logical signals such as empty, half-full, and full data like other general-purpose FIFOs, a timer interrupt can only be set based on its data transmission rate, FIFO capacity, and PCI bus speed. This timer interrupt is set to take approximately 14.8ms to send one frame of data from the data output card. This means that for every frame of data sent, the data output card will read one frame of data from the host computer's buffer. Since the data output card has already pre-read one frame before the timer interrupt is activated, even if there is a slight delay in the host computer's response to the timer interrupt, the FIFO will not be emptied. Furthermore, since the FIFO depth is 384K, approximately equivalent to 3 frames of data, it is impossible for the FIFO to be filled, resulting in data loss. The timer interrupt is precisely generated by the CPLD on the card based on the input clock. In the timer interrupt service routine, the program sequentially reads one frame of data from a complete spectral image. Once all 512 frames of data have been read, the pointer is reset to zero, and the process restarts from the beginning, ensuring the cyclical transmission of the spectral image data. Partial source code of the interrupt service routine is given below. WinDriver provides a large number of API functions for the PCI 9054 chip, making programming operations on the PCI 9054 very convenient. void WINAPI PLX_IntHandlerRoutine(P9054_HANDLE hPlx, P9054_INT_RESULT *intResult) — Interrupt service routine { DWORD dwIntStatus; P9054_DMAReadWriteBlock(hPlx, 0x0, (PVOID)pBuffer, SEND_BLOCK_SIZE, FALSE, P9054_MODE_WORD, P9054_DMA_CHANNEL_0); — Controls the PCI 9054 to read one frame of data from the host computer buffer in DMA mode if(block_num { pBuffer = pBuffer + SEND_BLOCK_SIZE; block_num++; } — After each frame of data is sent, the data pointer moves forward by the amount of data in one frame, and the count of sent frames is incremented by 1 else { pBuffer = Buffer; block_num = 0; —After 512 frames are sent, the pointer returns to zero, thus realizing the cyclic reading of 512 frames of data.} …… dwIntStatus = P9054_ReadReg (hPlx, P9054_INTCSR); P9054_WriteReg (hPlx, P9054_INTCSR, dwIntStatus | 0x00000d00); —Enable interrupts, interrupt service routine ends, waiting for the next interrupt.} 3. Test Results and Conclusions Installing the high-speed data output card on the computer and running the application program will enable the data output card to work. The following figure is a timing diagram of some signals on the data output card acquired by an oscilloscope. [align=center]Figure 5 Timing Diagram of Some Signals of PCI High-Speed ​​Data Output Card[/align] Wherein, LINTi# is the local interrupt input of PCI 9054, generated by the timer interrupt signal of CPLD; INTA is the PCI... The 9054 outputs an interrupt request signal on the PCI bus; WE is the write enable signal for the FIFO on the data output card, which writes data to the FIFO when it is valid; INT_EN is the timer interrupt enable signal, which controls the CPLD to start generating timer interrupts. As shown in the diagram, after pre-reading one frame of data, the timer interrupt enable signal becomes valid, and the CPLD starts sending a timer interrupt signal to the PCI 9054; after receiving this signal, the PCI 9054 immediately requests an interrupt from the host computer via the PCI bus; after a delay, the interrupt is responded to; in the interrupt service routine, the data output card reads data from the computer memory, and the time to read one frame of data is 14.6 ms. As can be seen from the timing diagram, the time for the data output card to read one frame of data (i.e., the WE signal validity time) is less than the time to send one frame of data (i.e., the timer interrupt interval), thus ensuring that the data in the FIFO is not emptied. Based on the above experimental results, it can be fully demonstrated that the high-speed data output card has achieved the design requirements. In the development process of the high-speed data output card, a dedicated PCI interface chip PCI was used. The 9054 and the WinDriver bus software development kit free us from the tedious and complex PCI protocol and low-level drivers, allowing us to devote more energy to hardware circuit design and software function implementation, greatly saving the development cycle. This card has been used in actual testing and has successfully completed the design requirements. References: [1]. Li Guishan, Chen Jinpeng. PCI Local Bus and Application. Xi'an University of Electronic Science and Technology Press, 2003 [2]. PCI Local Bus Specification, Revision 2.2. December 18, 1998 [3]. PCI 9054 Data Book, Version 2.1. http://www.plxtech.com January 2000 [4]. WinDriver v6.00 User's Guide. Jungo Ltd, 17th March 2003 [5]. Li Ailing, Zhang Boheng et al. Design of CCD Camera Image Signal Simulator Based on CPLD "Microcomputer Information" 2006, No. 1-2, pp. 151-152, p. 162