1. Introduction Brushless DC motors (BLDC) have advantages such as small size, no mechanical contacts, long lifespan, and easy installation, making them a research hotspot in motor applications. Currently, brushless motor control primarily uses Hall effect sensors as rotor position feedback elements. However, the presence of position sensors not only increases the size and cost of the motor but also significantly contributes to motor failure, reducing system reliability. Therefore, sensorless brushless motor control schemes have become a current research focus. In recent years, sensorless control technology using digital control has gradually become the future trend of brushless motor control. This paper designs a sensorless brushless motor controller using Actel's Fusion series mixed-signal FPGA as the controller core. The Fusion's proprietary 12-bit multi-channel high-speed A/D converter is used to detect the motor's back EMF. An embedded 51 soft core is used to implement a speed closed-loop control algorithm, successfully achieving a sensorless brushless motor control scheme. This scheme boasts advantages such as simple hardware design, high integration, high reliability, and high speed regulation accuracy. 2 System Design 2.1 Introduction to Fusion FPGA Actel Fusion series devices are the industry's first and only Flash architecture FPGAs with analog functionality, integrating an FPGA digital core, A/D converter, Flash memory, analog I/O, RTC, and other digital and analog components. Fusion devices internally feature 2-8 Mbit of user-available Flash memory and a 30-channel A/D converter with up to 12-bit precision and a sampling rate of up to 600 Ks/s. An on-chip 100 MHz RC oscillator, together with a PLL (phase-locked loop), provides the FPGA clock, saving the overhead of an external clock. These features greatly enhance the functionality of this series of FPGA devices, simplify system design, and significantly reduce board area and total system cost. When Fusion series FPGA devices are combined with software MCU cores such as 8051, Cortex-M1, and ARM7, true SoC systems can be implemented. Actel Fusion series FPGA devices represent the most comprehensive single-chip solution for analog and digital programmable logic systems to date. 2.2 Controller Design Based on the principle of brushless motor back EMF detection and combined with the internal functional characteristics of the Actel Fusion FPGA, a brushless motor control scheme as shown in Figure 1 was designed. In this design, the Fusion AFS600 serves as the controller core, using an embedded soft-core 8051 MCU to implement the control algorithm. A high-speed 12-bit A/D converter detects the back EMF of the three-phase windings and the external potentiometer setting voltage. The potentiometer setting voltage is used to determine the motor's rotation direction and speed. An LCD screen interface is implemented through FPGA logic to display the set speed and actual speed. Another important module is the three-phase PWM waveform generation module, implemented through a programmable counter. The PLL module provides a reference clock signal to the microcontroller, A/D converter, and PWM module. The peripheral circuits mainly include: an LCD1602 character LCD display, a potentiometer for setting the speed, and a brushless motor driver. The brushless motor driver uses an A3935 three-phase full-bridge device in conjunction with six high-power NMOS transistors (IRF2807S) to achieve a complete brushless motor control scheme. The back electromotive force of each winding is divided and filtered by series resistors before being fed into the internal A/D converter of the Fusion AFS600. The A3935 is an automotive-grade three-phase power MOSFET driver, particularly suitable for brushless motor control, featuring overvoltage, undervoltage, overcurrent, overheat, short circuit, and open circuit monitoring functions, offering powerful functionality and high reliability. 2.3 The three-phase PWM generation design utilizes Fusion logic gate circuits to implement a PWM generation module with continuously adjustable PWM frequency and duty cycle. The set frequency and duty cycle parameters can be converted into corresponding parameter values ​​based on the potentiometer voltage values ​​acquired by the A/D converter. Adjusting the external potentiometer generates six PWM signal waveforms with adjustable duty cycles. The relevant code below is a portion of the three-phase PWM source code written in VerilogHDL. Figure 2 shows the waveforms of two of the PWM signals measured with an oscilloscope. 2.4 Back EMF Detection The principle of back EMF detection is as follows: During the operation of a brushless DC motor, only two phase windings are in working state at any given time, meaning the power devices corresponding to these two phases are in PWM state, while the third phase is in a floating state, and its terminal voltage equals the induced electromotive force (EMF). The zero-crossing point of the back EMF occurs during the floating period of this phase winding. At this time, the zero-crossing point of the back EMF can be indirectly detected by detecting the terminal voltage. The back EMF detection of this controller uses the analog module inside the Fusion series FPGA device. The three-phase terminal voltages are filtered by resistor dividers and then sent to the 12-bit A/D converter inside the Fusion series FPGA device for time-division sampling. The Fusion series FPGA device uses a time-division cyclic sampling potentiometer to set the voltage and the back EMF voltage of the three-phase windings. The A/D converter stores the conversion results into the corresponding data registers. Figure 3 shows the waveforms of the actual back EMFs μ1 and μ2 measured by an oscilloscope in the cyclic sampling section of the A/D converter. Because the back EMF signal has undergone certain analog filtering processing, the signal-to-noise ratio is good, facilitating zero-crossing detection by the FPGA. 2.5 Control Software Design The PWM generation module and A/D converter cyclic sampling module mentioned above were written in Verilog HDL, compiled and called as modules in the Actel Libero IDE integrated development environment. The speed control algorithm was implemented using the 8051 soft core inside the Fusion series FPGA device, developed using Keil C. Figure 4 shows the algorithm flow of the 51 soft core. 3 Conclusion Based on the brushless motor controller hardware platform, the internal functional units of the FPGA were developed, compiled, linked, and pin-assigned. Experiments showed that smooth start-up and speed regulation of the brushless motor were achieved. The brushless motor used was powered by 24V and had a rated speed of 1600 r/min. The speed control range controlled by the FPGA controller was continuously adjustable from 760 to 1600 r/min. The implementation of this controller fully demonstrates the high integration of the Actel Fusion series mixed-signal FPGA in analog-to-digital mixed-signal system applications, truly showcasing the advantages of a single-chip SoC, and providing valuable reference for the application of Fusion series FPGA devices.