Abstract : This paper introduces the hardware design of a variable frequency speed control system based on DSP and IPM. The system employs a bootstrap circuit and uses a DSP to directly drive the IPM, resulting in a compact structure. The system has been put into mass production and has undergone several years of continuous operation. Actual operation demonstrates that the system is stable and reliable, meeting the application requirements.
Keywords : DSP; IPM; variable frequency speed control; hardware
introduction
Variable frequency speed control technology is widely used in industrial fields. With the continuous development of power electronic control technology and components, the integration and intelligence of variable frequency speed control systems are becoming increasingly higher, and the hardware structure is becoming more compact and simpler. DSP (Digital Signal Processor) + IPM (Intelligent Power Module) is one of the latest development directions of variable frequency speed control systems.
In the variable frequency speed control system composed of DSP+IPM, the high-speed operation and rich configuration of DSP and the simple control signal interface and comprehensive protection of IPM are fully utilized. This greatly reduces the number of system components and makes the structure more compact, while greatly improving performance and reliability, shortening the product development cycle and enhancing the product's competitiveness.
The variable frequency speed control subsystem I designed for a certain device adopted a DSP+IPM structure. The hardware design method of this system is described below.
Hardware design DSP and IPM
The system operates continuously for 24 hours. It requires control from a host computer to manage the start, stop, speed, and acceleration of two motors , while simultaneously feeding back power failure and fault signals to the host computer. The system must be compact, small in size, have comprehensive protection functions, and be stable and reliable. The system input voltage is 3Φ 200VAC. The power of the two controlled motors is 180W each. Based on these requirements, we adopted a DSP+IPM hardware architecture.
Because the system requires real-time control of two motors, we selected the TI TMS320L2407A DSP, specifically designed for motor control. This DSP utilizes high-performance static CMOS technology, with a clock frequency up to 40MHz and an instruction cycle of only 25ns, enabling a low-power design of 3.3V to meet real-time control requirements. Particularly noteworthy is its dedicated peripheral configuration for motor control—two event management modules, EVA and EVB. Each module includes: two 16-bit general-purpose timers; eight 16-bit PWM channels; three external event time stamp capture units; a programmable dead time to prevent shoot-through failures; an on-chip position encoder interface circuit; and a synchronous A/D converter, facilitating the control of two motors. Furthermore, this DSP features up to 40 individually programmable composite general-purpose input/output pins and up to five external interrupts, greatly simplifying practical applications.
Because the system's input voltage is 3Φ 200VAC, and the power of each of the two controlled motors is 180W, considering an appropriate margin, we selected Mitsubishi's third-generation DIP-IPM PS21563 (10A/600V). The Mitsubishi DIP-IPM is a small, intelligent power module designed for AC100～200V small-capacity motor inverter drives, employing a transfer-type package structure and integrating power circuitry and drive protection circuitry into one unit. It has the following characteristics:
The 3-phase AC inverter output circuit is equipped with Mitsubishi's 5th generation planar IGBT and CSTBT (Carrier Stored Trench-gate Bipolar Transistor) power chips to achieve lower losses.
• It adopts a bootstrap circuit structure, which can achieve single power supply drive.
It has a built-in IGBT driver circuit with overload protection and control power undervoltage protection. The P-side has UV (control power undervoltage) protection but does not output a fault signal F. The N-side has UV and SC (overload) protection and outputs a fault signal F.
• Built-in dedicated HVIC (high voltage 600VIC), eliminating the need for isolation circuits (such as optocouplers), and can be directly driven by DSP or 3V-level microcontroller.
The input interface circuit adopts high-level drive logic, which eliminates the timing requirements of power-on and power-off of the old low-level drive method and enhances the module's self-protection capability.
The system input is 3Φ 200VAC, which is rectified by a three-phase full-bridge rectifier to approximately 270VDC to supply the IPM. The 270V is then converted from DC to DC to generate auxiliary power, providing control power to the DSP, host computer, and IPM modules. The host computer receives control from the main system and sends two control signals to the DSP for motor start/stop, four acceleration levels, and eight speed levels. The DSP generates two sets of six pulses based on the host computer's control signals to control the two IPM modules respectively, thereby controlling the start/stop, acceleration, and speed of the two motors. The speeds of the two motors are fed back to the host computer via shaft encoders. Fault signals from the IPMs are fed back to the DSP, which then feeds back fault signals and power-down signals to the host computer. The system block diagram is shown in Figure 1.
Figure 1 System principle block diagram
Bootstrap circuit
In typical inverter circuits, the trigger pulses of the three IGBTs in the upper arm have a floating reference ground, requiring three sets of isolated power supplies. The trigger pulses of the three IGBTs in the lower arm share a common reference ground, requiring only one power supply. Therefore, a total of up to four sets of isolated power supplies are needed. Mitsubishi's DIP-IPM, however, uses a bootstrap circuit structure, easily enabling single-supply drive. Its specific working principle is as follows: When the DIP-IPM starts, it first sends a sufficient number of charging pulses or a sufficiently wide single pulse to the lower arm IGBTs to turn them on (N-side). This allows the lower arm's power supply to fully charge the three bootstrap capacitors in the upper arm through the IPM's internal charging path, thus powering the trigger pulses of the three IGBTs in the upper arm. Only then does it begin sending PWM control pulses. The bootstrap circuit charging path and timing diagram are shown in Figure 2.
Figure 2. Charging path and timing diagram of the bootstrap circuit
The formula for calculating the value of the bootstrap capacitor C1 is C1 = IBS × T1 / ΔV, where T1 is the maximum on-state (ON) pulse width of the upper IGBT, IBS is the drive current of the IC (considering temperature and frequency characteristics), and ΔV is the allowable discharge voltage. Note that the bootstrap capacitor value calculated using this formula should be the minimum value, and a certain margin should be added when selecting it in practice.
The value of the bootstrap resistor R2 should be selected to meet the following condition: the time constant R2 × C1 should be sufficient to charge the discharge voltage (ΔV) onto C1 within the minimum conduction pulse width (T2) of the lower arm IGBT. That is, R2 = {(VD - VDB) × T2} / (C1 × ΔV), where VD is the power supply voltage and VDB is the voltage across the bootstrap capacitor C1.
Bootstrap diode selection: For a 3Φ 200VAC circuit, if the power input voltage fluctuation range is ±30%, then the DC voltage after three-phase full-bridge rectification is VD = 200 x 1.3 x 1.35 = 351 (V). Taking a minimum margin of 1.5, the bootstrap diode's withstand voltage should be 351 x 1.5 = 526.5 (V), which is 600V. Therefore, the minimum rated voltage of the bootstrap diode should be 600V. Because the PWM carrier frequency is relatively high (maximum 20kHz), a fast recovery diode (reverse recovery time less than 100ns) is recommended.
Hardware Design Essentials
Based on my experience in designing this system, the hardware design should pay attention to the following aspects to improve the system's anti-interference capability and enable it to operate reliably and stably in a highly interfering industrial environment.
Although the DIP-IPM module can be directly driven by the DSP, during actual debugging, it was found that the DSP pins sometimes exhibit uncertain states during power-on and flash programming, generating interference pulses that cause the upper and lower IGBT arms of the IPM to shoot through, triggering short-circuit protection. Therefore, we added an eight-channel, dual-supply, three-state gate converter transceiver chip 74LVC4245 to each of the two trigger pulse channels from the DSP to the IPM. The output enable terminal of this chip is controlled by a simple logic gate circuit, as shown in Figure 3. This ensures that interference pulses will not falsely trigger the IPM during power-on and flash programming of the DSP.
Figure 3. Logic gate circuit for controlling the on/off state of the trigger pulse channel.
To prevent signal oscillation, an RC decoupling circuit should be added to each input terminal. For the two sets of trigger pulses, the RC circuit can filter out interference pulses and limit the minimum pulse width of the input pulses. The RC capacitance should be matched with the PWM carrier frequency to filter out interference signals without distorting the trigger pulses. Because the DIP-IPM input IC has a built-in 2.5KΩ (min) pull-down resistor, the value of R in the RC circuit should be chosen to ensure that the signal value after voltage division meets the input level threshold requirements of the DIP-IPM.
The DIP-IPM also has a very practical function: short-circuit protection. During the software debugging of this system, this function proved effective multiple times, reliably protecting the modules and ensuring that none of the IPM modules were damaged during the prototype debugging process. However, to ensure this function functions reliably, the following two points should be noted:
1) An RC filter circuit must be installed in the signal loop of the external current sensing resistor to prevent false short-circuit protection operation. The selection of the RC time constant should take into account the hard interrupt capability of the IGBT, and is generally recommended to be 1.5~2μS, with a maximum of 6μS. Too short a time constant may cause false short-circuit protection operation, while too long a time constant may exceed the tolerance capability of the IPM module and fail to effectively protect the IPM module.
2) The external current sensing resistor should be a non-inductive resistor. The wiring of this resistor and its signal lead to the corresponding pin of the IPM module should be as short as possible to avoid short circuit protection malfunction caused by interference from lead inductance.
The following anti-interference measures should be taken when laying out PCBs:
1) The high-voltage (power section) and low-voltage (control section) circuits are separated by area.
2) Digital ground (control ground) and analog ground (power ground) should be laid out separately and connected only at one point. Care must be taken to prevent current from flowing through the control ground wire to avoid introducing ground interference.
3) Slots can be opened between adjacent trigger pulse pins of the IPM module on the PCB to avoid mutual interference.
4) The wiring from the current sensing resistor and its signal line, the trigger pulse signal and all capacitors to the IPM module should be as short as possible to minimize interference caused by the lead inductance.
Conclusion:
Thousands of units of this system have been mass-produced and have been running continuously in the field for over three years. Actual operation has shown that the system is stable and performs well. It can be predicted that the DSP+IPM mode will be one of the development directions for compact variable frequency speed control systems.
References:
[1] TMS320LF2407A DSP controller, TI, 2002
[2] DIP-IPM version 3 Application Technical Data, Mitsubishi Electric Corporation, 2003
