Introduction The CAN bus, with its low development and maintenance costs, high bus utilization, long transmission distance (up to 10 km), and high transmission rate (up to 1 Mbps), enables users to build stable and efficient fieldbus networks. The CAN bus has been widely used in various automated control systems, such as automotive electronics, automatic control, intelligent buildings, power systems, and security monitoring. With the expansion of the CAN bus network area, direct data transmission between two nodes will be insufficient to meet the requirements of long-distance communication. CAN repeaters are relay stations that extend the communication distance of the CAN bus, and their communication efficiency and reliability directly affect the communication capability of the CAN bus. Traditional CAN repeaters based on a single MCU cannot meet the requirements of relaying large amounts of data. This paper designs a high-performance CAN bus repeater based on a dual-MCU architecture. 1 System Overall Design The CY7C136 is a 2 KB high-speed CMOS static RAM. The same RAM has two sets of data lines and two sets of address lines. The control of each port is independent, and data can be accessed at any location in the memory. The dual-port RAM serves as a shared resource for the two MCUs; one port is connected to MCU1, and the other port is connected to MCU2. Data received from SJAl000CAN bus interface 1 is sent to the dual-port RAM. This data is then retrieved by MCU2 and sent to SJAl000 CAN bus interface 2. Data received from SJAl000 CAN bus interface 2 is also sent to the dual-port RAM and retrieved by MCU1 and sent to SJAl000 CAN bus interface 1. Since the address bus and data bus of the MCU are multiplexed, a latch is used for address latching. The overall hardware structure is shown in Figure 1. 2 Hardware Circuit Implementation The two MCUs used in the circuit are AT89C52 8051 series microcontrollers, which are low in cost, have a short development cycle, are easy to implement, and have high reliability. MCU1 and MCU2 communicate and respond through P1.5, P1.6, and P1.7 of port P1 to ensure the security of system memory access. 2.1 MCU Main Control Circuit MCU1 (AT89C52 chip 1) is connected to the dual-port RAM and CAN bus controller. To prevent address conflicts, a 74LS138 decoder is used for address decoding. The PO port of the AT89C52 is an address/data multiplexed port, using a 74HC573 as the address latch. Since the circuit principles of MCU1 and MCU2 are the same, this paper only introduces the control circuit of MCU1. The circuit principle of MCU1 is shown in Figure 2. 2.2 Dual-Port RAM Interface Circuit The dual-port RAM circuit interface is shown in Figure 3. The dual-port RAM chip CY7C136 acts as a data relay station for the two MCUs, connected to the corresponding pins of the two MCUs respectively. Specifically, pins I/O0L to I/O7L of the CY7C136 are connected to the PO port of the first AT89C52 (MCU1), and pins I/OOR to I/O7R are connected to the second AT89C52 (MCU2). YOAOUT is the chip select signal for MCU1 to read and write the dual-port RAM, and Y1AOUT is the chip select signal for MCU2 to read and write the dual-port RAM. The MCU's read/write control signal lines are connected to the corresponding read/write control signal lines of the dual-port RAM. 2.3 CAN Bus Controller Interface Circuit The CAN bus controller uses the SJAl000. The YO pin output of the 74LS138 decoder is used as the chip select signal for the SJAl000. The interrupt pin is connected to the MCU1's INTO pin as the trigger signal for handling CAN receive interrupts. The circuit principle is shown in Figure 4. 3 Software Design and Implementation 3.1 Memory Space Allocation To achieve the highest efficiency of the dual-port RAM, the 2KB memory space is designed as two 1KB circular queues. The structure of each circular queue is shown in Figure 5 (the shaded area is the area containing data, and the unshaded area is the free area). 3.2 Program Control Flow The repeater only relays data from the bus, and this data is random; therefore, reception is done via interrupts. At any given moment, as long as the SJAl000 successfully receives a frame of data, it requests an interrupt from the MCU responsible for this port to receive the data and send it to the circular queue. When there is data to be sent in the circular queue, the program processing flow is shown in Figure 6 (where tail and head are the tail and head pointers of the circular queue, respectively). The MCU first obtains information from the other party's circular queue, mainly checking if the circular queue is empty. If it is empty, no operation is performed. If it is not empty, there is information to be sent in the queue, so a message transmission is initiated. If the transmission is successful, the other party is notified to modify the circular queue pointer via a handshake signal. 4. Testing A stress test (high data load rate test) was performed on the dual-MCU repeater based on dual-port RAM. 10,000 frames of data were loaded onto the two CAN ports over a short distance to test the repeater's successful relaying. The results are shown in Table 1 (the table data represents the number of successfully relayed frames). According to CAN bus specifications, its average load rate should not exceed 65%, and the average load rate of traditional single-MCU CAN repeaters is difficult to reach 60%. As can be seen from Table 1, the performance of the CAN repeater is greatly improved after introducing dual MCUs, enabling stable operation even under load rates exceeding 60%. The circular queue overflow problem can be solved by increasing the size of the dual-port RAM. Conclusion The design of a CAN bus repeater using dual MCUs and dual-port RAM solves the problem of a single MCU's inability to quickly handle excessive CAN bus load, greatly improving its performance and efficiency. This provides a good technical platform and solution for the optimized design of CAN repeaters in the engineering field.