1 Introduction With the development of internet technology, leaps and bounds have been brought about in many fields. A new trend in embedded system applications is the integration of network communication functions into embedded devices, such as network monitoring and network data acquisition systems, to facilitate information exchange with remote devices and enhance system interconnectivity. A single network cable is all that's needed to easily interconnect the systems. Currently, there are many types of embedded processors on the market. Altera has launched the second-generation on-chip programmable embedded soft-core processor, Nios II, coupled with its low-cost, high-performance FPGA devices, making embedded system development increasingly convenient. Furthermore, due to the configurable nature of Nios II and the programmable nature of FPGA devices, it offers significant advantages in flexibility compared to dedicated hardware, leading to the widespread application of FPGA devices in modern electronic design. 2 System Design 2.1 Introduction to Nios II The Nios II embedded soft-core processor is Altera's second-generation on-chip programmable soft-core processor. Nios II is configurable, allowing users to configure the processor according to their actual needs to achieve efficient resource utilization. Its performance can exceed 200 dMIPS. Nios II employs a Harvard architecture, featuring a 32-bit instruction set, a 32-bit data channel, and configurable instruction and data buffers. It also supports user-defined instructions (up to 256) to extend the CPU instruction set and improve system performance, providing a complete solution for System-on-a-Chip (SOPC) design. Nios II offers three kernels: Nios II/F, a high-performance kernel that is the fastest but consumes the most resources; Nios II/E, a low-cost kernel that is the slowest but consumes the fewest resources; and Nios II/S, a kernel that strikes a balance between performance and cost. This design uses the Nios II/S kernel. The advantage of Nios II lies in its flexibility, allowing for flexible configuration and customization according to user needs. System design based on the Nios II soft core utilizes Altera's SOPC Builder system design tool and the Nios II IDE integrated development environment for co-design of hardware and software, significantly shortening the development cycle and allowing for convenient system modifications at any stage of development. The abundant logic resources of FPGA devices, combined with the powerful processing capabilities of Nios II, will provide an effective solution for embedded system design. 2.2 System Design [align=center] Figure 1 System Module Diagram[/align] The system module diagram is shown in Figure 1. The design uses Altera's Cyclone II series chips. A Nios II soft-core processor is configured within it to control the operation of peripheral devices and the protocol stack. Furthermore, a user instruction (cal_checksum) for calculating the checksum is added. The on-chip RAM is used for program execution; the flash memory uses Sharp's LH28F160S3T-L13A to store programs and configuration information. After system power-on, the program is first copied from the flash memory to the on-chip RAM for execution; the network interface chip uses SMSC's 10/100M Ethernet interface controller chip LAN9C111. Therefore, when configuring the system in SOPC Builder, the LAN9C111 interface controller provided free by Altera needs to be added. Embedded devices can access the Ethernet network and communicate with other devices on the network through the LAN9C111; the SDRAM uses Micron's MT48LC8M16A2 to cache network data, and the SDRAM controller uses Altera's free SDRAM controller. To improve system performance, one approach is to increase the processor's processing power; another is to implement time-consuming modules in software using hardware modules. Analysis revealed that the most time-consuming part of the network protocol stack operation is checksum calculation, especially when the data volume is very large. To address this, a custom-designed hardware instruction for checksum calculation (cal_checksum) was created to accelerate data checksum calculation. This instruction was added to the NiosII system and called within the protocol stack to shorten checksum calculation time, improve processing speed, and ultimately enhance system performance. 2.3 Checksum Calculation Instruction (cal_chkusm) As mentioned in the analysis above, the most time-consuming part of the entire protocol stack processing is data checksum calculation, especially when the data length is large. Therefore, the data checksum calculation is implemented in hardware as a user-defined instruction in NiosII to improve calculation speed. During the protocol stack porting process, the data width was modified to 16 bits to facilitate adding the 16-bit checksum calculation result to the corresponding field. Since checksum calculation requires many clock cycles to complete, the checksum calculation instruction uses a multi-cycle user instruction structure. The multi-cycle user instruction's port operations include fixed-length and variable-length operations. Because the data length transmitted over the network is constantly changing, the checksum calculation instruction uses a variable-length operation, which also affects the selection of port signals. The signals in the multi-cycle user instruction structure are: reset, clk, clk_en, start, dataa[31:0], datab[31:0], done, and result[31:0]. Except for reset, clk, and clk_en, the other signals are optional and should be selected based on the specific application. In this design, the checksum calculation instruction uses start, dataa[31:0], done, and result[31:0]. The start signal serves as the data valid signal, and dataa[31:0] is the data input signal. When the checksum calculation is complete, the done signal becomes valid, notifying the CPU to read the data on the result port. Therefore, the checksum calculation instruction logic must ensure that the data on the result port is valid when the done signal is valid. Add checksum calculation instructions in SOPC Builder, then rebuild the system, update and compile in Quartus II, and recompile the project in the IDE. The "system.h" file in the system library contains the macro definition of the checksum calculation instructions as follows: #define alt_ci_cal_chksum_n 0x00000000 #define alt_ci_cal_chksum(a) __builtin_custom_ini(alt_ci_cal_chksum_n,(a)) Users only need to replace the checksum calculation part with the above macro in the source file. This is very simple for users, just like calling a sub-function. It can be seen that the embedded system developed based on the Nios II soft core processor has advantages that general embedded processors cannot match. 3 Software Design The protocol stack uses UIP, which is now very mature in the field of embedded applications. If the LWIP protocol stack provided by Altera is used, then its porting to the embedded operating system must be considered, which will undoubtedly increase the complexity of the system software design and the amount of code. A key part of the design is the porting of the UIP protocol stack to Nios II. Taking into account the characteristics of Nios II, UIP is modified appropriately to fully utilize the processing power of the Nios II processor and improve system performance. Originally designed for 8-bit processors, UIP has been modified to 16-bit, theoretically doubling the processing power and thus doubling the system performance. Based on the TCP/IP model structure, the data link layer and physical layer are handled by the LAN9C111 network interface chip; network layer and transport layer protocol parsing are implemented in Nios II using an embedded TCP/IP protocol stack; the application layer is written by the user as needed. All modules work together to complete the network communication function. 3.1 Writing the Low-Level Driver The low-level driver for the LAN9C111 chip is provided free of charge by Altera. These low-level drivers can be called to complete communication functions such as initialization, communication establishment, and listening. These low-level driver functions are already encapsulated, and users do not need to understand their details to write network communication programs. However, for advanced development, a certain understanding of the overall program's working mechanism is necessary. Several key low-level driver functions handle startup, reset, and PHY initialization, Ethernet packet transmission and reception, and interrupt handling: `static void r_lan91c111_enable()`: Enables chip operation, allowing transmission and reception. `int nr_lan91c111_reset()`: Resets the chip. `static int r_lan91c111_init_phy()`: Initializes the physical layer chip. `int nr_lan91c111_set_irq()`: Sets the chip's interrupts. Upper-layer communication programs call these functions to control the network interface; communication functionality is based on this. 3.2 Communication Software Implementation The communication software performs the main functions of communication between devices, primarily using the UIP protocol stack. The transport layer implements TCP and UDP, requiring different considerations in software design. Different data transmission requirements necessitate different transport layer protocols. For example, applications with high real-time requirements require connectionless UDP; applications with lower real-time requirements but needing reliable data transmission use connection-oriented, reliable TCP to ensure transmission reliability. The program framework is as follows: main() { netif_init(); // Network interface initialization uip_init(); // Protocol stack initialization arp_table_init(); // ARP table initialization netconn_new() // Establish a new connection netconn_bind() // Bind port number netconn_listen() // Listen to port while(1) { if (data received) { ... // Process the received data} else if (data sent) { ... // Send data} else ... // Return to prepare for the next processing} } Figure 2 is the software processing flow. [align=center] Figure 2 Communication software flowchart[/align] 4 Conclusion The system design using NiosII, due to the powerful system development functions of the SOPC Builder tool and the NiosII IDE integrated development environment, makes the system design simple and convenient, highly scalable, and the system software design and system design are carried out simultaneously, greatly shortening the development cycle. The design of this network platform utilizes the mature and open-source UIP (User Interface Package) from the embedded systems field, making its porting very convenient. Modifications are made to maximize the performance of the Nios II processor, and the addition of simple and flexible user-defined instructions significantly improves system performance. This system has been hardware-verified, demonstrating reliable and stable network communication, and has been applied to a data processing system requiring remote network communication capabilities.