Abstract: Research on robot visual servoing systems is an important aspect of the robotics field, and its findings can be directly applied to problems such as automatic obstacle avoidance, trajectory tracking, and moving target tracking. This paper addresses the requirements of speed and accuracy in robot visual servoing systems by designing a robot visual image processing system based on the TMS320C6201 and analyzing the fundamental principles of the robot visual servoing method based on the image Jacobian matrix. Keywords: visual servo; image processing; TMS320C6201; real-time; image Jacobian matrix [b][align=center]Research on Robot Visual Servo System based on DSP JIANG Xing-hong , LI Zheng-ming[/align][/b] Abstract: Robotic visual system is one of the most important subjects in the field of robot. Its research findings can be directly applied to robot obstacle avoidance, trajectory tracking, and moving object tracking, etc. In this paper, based on the characteristics of robot visual servo system, a real-time image processing system based on TMS320C6201 is introduced, and the principle for robot visual servo system based on image Jacobian matrix is ​​analyzed. Keyword: visual servo; image processing; TMS320C6201; real-time; image Jacobian matrix 1. Introduction Robot visual servo system is an important research direction in the field of robotics. Originating in the early 1980s, it has made great progress with the development of computer technology, image processing technology, and control theory, and some systems have been put into use. Visual servoing differs from conventional machine vision. Visual servoing utilizes the principles of machine vision to automatically acquire and analyze images. It rapidly processes the image feedback information obtained directly, providing feedback signals in the shortest possible time to form a closed-loop control system for the robot's position, thus achieving robot control. Because the system aims to achieve a specific control function, the image processing in a visual servoing system must be fast and accurate. This paper focuses on the fast and accurate requirements of robot visual servoing systems and discusses and studies DSP-based image feedback robot visual servoing technology to meet the needs of the research project. 2. System Working Principle and Hardware Composition Image-based visual servoing directly calculates image errors, generates control signals, and transforms them into the robot's motion space to drive the manipulator and complete the servoing task. This method is insensitive to calibration errors and spatial model errors. For robot visual servoing systems, real-time performance has always been a significant and difficult problem to solve. Low image acquisition speeds and long image processing times introduce significant time lags into the system; furthermore, the introduction of visual information significantly increases the computational load. Image processing speed is one of the main bottlenecks affecting the real-time performance of visual servoing systems. The challenge of real-time image processing design lies in processing large amounts of image data within a limited time. From the perspective of human vision theory, only an image processing system with a processing speed of 25 frames per second or higher can achieve real-time performance. This means the real-time image processing system must complete the processing of one frame within 40ms to ensure real-time image quality. To achieve this processing speed, we adopted a DSP-based image visual servoing method, the structure of which is shown in Figure 1. [align=center] Figure 1: DSP-based image feedback robot visual servoing structure[/align] 2.1 Introduction to the WTC6201PA Board This paper uses the WTC6201PA board from Wenting Company, and its hardware composition is shown in Figure 2. [align=center] Figure 2: Hardware composition of the WTC6201PA board[/align] The WTC6201PA board is a type of EVM board, and it uses the TI TMS320C6201 DSP chip. The TMS320C6201 chip has a maximum clock frequency of 200MHz and can execute up to 8 instructions per clock cycle, achieving a fixed-point arithmetic capability of 16000MIPS. Its main features include: * A modified Harvard bus architecture with independent program, data, and DMA buses, allowing for parallel instruction fetching, data reading/writing, and DMA operations. * Pipeline processing, enabling overlapping execution of two or more different operations, improving program execution speed. * A high-performance external memory expansion interface (EMIF) that can directly connect to Synchronous Burst Static Memory (SBSRAM) and Synchronous Dynamic Memory (SDRAM) for large-capacity, high-speed storage; it also includes a Direct Asynchronous Memory (DAM) interface for connecting to SRAM and EPROM for small-capacity data and program storage; the integrated 64K program memory can be configured as a CASHE to improve program execution efficiency. * A 16-bit host port allows communication with other CPUs' memory areas and peripheral circuits. Furthermore, the multi-channel DMA controller can perform data transfer within mapped memory space without CPU intervention, reducing the CPU's workload. The board is equipped with high-speed synchronous memory SBSRAM (128K×32Bit) and SDRAM (4M×32bit), two A/D converters, a large-capacity FPGA device, and external I/O interfaces. It also provides a McBSP interface compatible with 5V TTL levels for easy communication with external systems. The WT6201PA board meets the PCI Local Bus Revision 2.1 protocol, allowing the host to access all DSP resources and enabling users to load programs via the host. The WTC6201PA board provides driver software for Win98 and NT, as well as DSP application software (APIs). Utilizing this hardware platform and underlying software library, users can easily develop software. 2.2 System Hardware Implementation We selected the TMS320C6201 chip, FPGA, SBSRAM, SDRAM, dual-port RAM, PCI bus, and JTAG interface on the WTC6201PA board as the vision image processing unit. This unit, along with a PC host, image acquisition card, CCD camera, and robot control system, forms the system. The block diagram is shown in Figure 3. [align=center]Figure 3 System Principle Block Diagram[/align] The system operation process is as follows: The CCD camera outputs a standard full television signal, which includes seven signals: image signal, composite synchronization signal, horizontal and vertical blanking signals, slot pulse, and front and rear equalization pulses. This system uses the DH-PCI-H image acquisition card from Beijing Daheng Company to perform video signal preprocessing. The CCD camera inputs video data to the image acquisition card, which acquires video data according to the set window position, size, and mode. The acquired data is stored in the computer's memory. Image transmission is controlled by the image card and does not require CPU participation; the image transmission speed can reach 40MB/s. The image acquisition mode of the image acquisition card is set to continuous acquisition at 25 frames/s, so the acquisition time for one frame is 40ms. Each frame consists of two fields, odd and even, with a field frequency of 50Hz, meaning the scanning time for one field is 20ms. The image acquisition size is 512×512 pixels, quantized to 8 bits, with 256 gray levels, so the data size of one frame is 512×512×8bit=256KB. Image data is stored interlaced, meaning odd and even field image data are interleaved to form a complete image frame. The C6201 uses BOOTMODE[4:0] to set the chip's boot mode, and the loading process uses the host (HPI) boot method. The external host initializes the CPU's memory space through the host port. After completing all initializations, the host sets the DSPINT bit in the host port control register to 1, ending the boot process. The CPU exits the reset state and begins executing the instruction at address 0. After the system powers on, the host initializes the system through the HPI port, mainly setting various registers, including EMIF, interrupt, DMA, and other related register initialization operations. The host writes 1 to the DSPINT bit in the HPI control register to trigger DSP operation, and the system enters a waiting state. The CCD camera acquires images in real time, which are processed by the image acquisition card and stored in the host memory. When the PC's memory buffer is full, it sends an interrupt signal to the DSP. After the DSP responds, it transfers the image data from the host memory to the external SDRAM of the WTC6201PA board via the PCI bus through the HPI port. The image data within the DSP control gate range is transferred to the internal data memory using DMA. Since DSP is an instruction set processing chip, it has advantages such as good programmability and the ability to process a large number of complex instructions (determined by the size of the program RAM address space), but its processing speed is relatively slow compared to FPGA; while FPGA is a programmable logic device, which has strong fine-grained parallel processing and multi-level pipeline processing capabilities, but its limited internal logic resources make it unsuitable for implementing complex logic operations. Therefore, we use FPGA as a coprocessor to complete the low-level operations, and then DSP to complete the high-level operations. The two operations can be run in parallel in a pipelined manner to jointly complete high-speed image processing. Image data transmission between FPGA and DSP uses dual-port RAM. After processing a frame of image, DSP sends information to the host. After the host responds, it transmits the image processing result to the PC memory via the PCI bus. The PC then sends the position deviation data signal to the servo control system to complete the servo task. 3 Image Jacobian Matrix For the control mechanism of the image feedback robot visual servo system, the image Jacobian matrix is ​​very important. It describes the relationship between the motion in the robot space and the motion in the image feature space: Equations (2) and (4) are two representations of the image Jacobian matrix, which are the basis for the research of visual tracking based on image feedback. It should be noted that, to ensure a unique image feature vector, the dimension of the image feature space should be greater than or equal to the dimension of the pose space (n≧m). Methods for calculating the image Jacobian matrix include online estimation, empirical methods, and learning methods. Online estimation obtains the image Jacobian matrix through dynamic estimation; empirical methods can obtain the image Jacobian matrix through calibration or prior model knowledge; learning methods mainly utilize offline teaching and neural network methods to obtain the Jacobian matrix. Conclusion This paper analyzes the basic principles of robot vision servoing systems and designs a vision system based on the TMS320C6201 and a programmable logic device (FPGA) coprocessor structure, realizing real-time image acquisition and target processing. In the laboratory, we built an experimental platform using the designed vision system, and the experiments verified that the designed vision system meets the real-time requirements of robot vision servoing systems. The author's innovation: For robot vision servoing systems, real-time performance has always been a difficult and important problem to solve. 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